Modeling low-frequency electrode-type resistivity tools in invadedthin beds

The authors formulate and implement a numerical mode-matching (NMM) method to model electrode-type resistivity tools in invaded thin beds. The authors derive the low-frequency approximation of the Maxwell's equations to obtain the partial differential equation for the potential field. The new NMM program is validated by comparing the numerical results with those obtained from other dc programs. It is found that this new program is much faster than the program using the finite-element method (FEM), and hence is useful for routine interpretation of resistivity logs and for inversion     

Classification of pixels in a noisy grayscale image of polar ice

Often, in synthetic aperture radar (SAR) images of polar ice, one encounters shadow-like features across the images. Such features make it difficult to classify pixels into ice and water. Accordingly, it becomes a challenge to determine the true size and boundaries of ice floes in an SAR image of polar ice. We develop a simple statistical procedure which classifies pixels of an image by eliminating the effects of shadow-like features. Methodology developed in this paper is illustrated using some noisy SAR images of ice floes in the Arctic sea.     

Controller for digital audio power amplifier with bit stream input

A new controller for a digital audio amplifier with bit stream input is proposed. The proposed controller has excellent features such as wide error correction range and no limitation on the modulation index. The controller is implemented in the half-bridge class-D amplifier and performance is verified through experiments.     

Physical model of drain conductance, gd, degradation ofNMOSFET's due to interface state generation by hot carrierinjection

Degradation of analog device parameters such as drain conductance, g_d, due to hot carrier injection has been modeled for NMOSFET's. In this modeling, mobility reduction caused by interface state generation by hot carrier injection and the gradual channel approximation were employed. It has been found that g_d degradation can be calculated from linear region transconductance, g_m, degradation which is usually monitored for hot carrier degradation of MOSFET's. The values of g_d degradation calculated from g_m degradation fit well to the measured values of g_d degradation The dependence of the g_d degradation lifetime on L_eff has been also studied, this model also provides an explanation of the dependence on L_eff. The model is then useful for lifetime predictions of analog circuits in which g_d degradation is usually more important than g_m degradation     

A simulated annealing algorithm for resource constrained project scheduling problems

This paper presents a simulated annealing algorithm for resource constrained project scheduling problems with the objective of minimising makespan. In the search algorithm, a solution is represented with a priority list, a vector of numbers each of which denotes the priority of each activity. In the algorithm, a priority scheduling method is used for making a complete schedule from a given priority list (and hence a project schedule is defined by a priority list). The search algorithm is applied to find a priority list which corresponds to a good project schedule. Unlike most of priority scheduling methods, in the suggested algorithm some activities are delayed on purpose so as to extend search space. Solutions can be further improved by delaying certain activities, since non-delay schedules are not dominant in the problem (the set of non-delay schedules does not always include an optimal solution). The suggested algorithm is flexible in that it can be easily applied to problems with an objective function of a general form and/or complex constraints. The performance of the simulated annealing algorithm is compared with existing heuristics on problems prepared by Patterson and randomly generated test problems. Computational results showed that the suggested algorithm outperformed existing ones.     

Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers

A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V//spl mu/s for a load capacitance of 1 nF almost independently of static currents as low as 1 /spl mu/A, this buffer amplifier is promising for column driver ICs of flat panel displays that require low static power consumption, high current driving capabilities, and small silicon areas.     

A new MMIC broadside coupler using an array of air-bridges for directivity enhancement

A new quadrature broadside coupler is proposed, which employs an array of air-bridges to enhance directivity via its phase-equalization effect on the c-mode and /spl pi/-modes. The realization of air-bridges follows a standard MMIC fabrication process. An experimental chip fabricated on the 75-/spl mu/m GaAs substrate verifies the air-bridge effect and shows wideband characteristics of the coupling of 3.2/spl plusmn/0.4 dB, the insertion loss of 3.9/spl plusmn/0.4 dB, the output phase deviation from quadrature less than 6/spl deg/, and the isolation greater than 18 dB from 20 to 40 GHz.     

Test data compression and test time reduction using an embedded microprocessor

Systems-on-a-chip (SOCs) with many complex intellectual property cores require a large volume of data for manufacturing test. The computing power of the embedded processor in a SOC can be used to test the cores within the chip boundary, reducing the test time and memory requirements. This paper discusses techniques that use the computing power of the embedded processor in a more sophisticated way. The processor can generate and reuse random numbers to construct test patterns and selectively apply only those patterns that contribute to the fault coverage, significantly reducing the pattern generation time, the total number of test applications and, hence, the test time. It can also apply deterministic test patterns that have been compressed using the characteristics of the random patterns as well as those of the deterministic patterns themselves, which leads to high compression of test data. We compare three fast run-length coding schemes which are easily implemented and effective for test-data compression. We also demonstrate the effectiveness of the proposed approach by applying it to some benchmark circuits and by comparing it with other available techniques.     

A graphic approach to performance analysis of multistage linear interference canceller in long-code CDMA systems

The signal-to-interference-plus-noise-ratio performance of the multistage linear parallel and successive interference cancellers (LPIC and LSIC) in a long-code code-division multiple-access system is analyzed using a graphical approach. The decision statistic is modeled as a Gaussian random variable, whose mean and variance can be expressed as functions of moments of R for the LPIC and L for the LSIC, respectively, where R is the correlation matrix of signature sequences and L is the strict lower triangular part of R. Since the complexity of calculating these moments increases rapidly with the growth of the stage index, a graphical representation of moments is developed to facilitate the computation. Propositions are presented to relate the moment calculation problem to several well-known problems in graph theory, i.e., the coloring, the graph decomposition, the biconnected component finding, and the Euler tour problems. It is shown that the derived analytic results match well with simulation results.     

Computational Implementation of Asymmetric Integral Imaging by Use of Two Crossed Lenticular Sheets

We propose an asymmetric integral imaging method to adjust the resolution and depth of a three‐dimensional image. Our method is obtained by use of two lenticular sheets with different pitches fabricated under the same F/#. The asymmetric integral imaging is the generalized version of integral imaging, including both conventional integral imaging and one‐dimensional integral imaging. We present experimental results to test and verify the performance of our method computationally.