Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

A 0.25-/spl mu/m CMOS quad-band GSM RF transceiver using an efficient LO frequency plan

This paper describes a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS applications. It is the most important design issue to maximize resource sharing and reuse in designing the multiband transceivers. In particular, reducing the number of voltage-controlled oscillators (VCOs) required for local oscillator (LO) frequency generation is very important because the VCO and phase-locked loop (PLL) circuits occupy a relatively large area. We propose a quad-band GSM transceiver architecture that employs a direct conversion receiver and an offset PLL transmitter, which requires only one VCO/PLL to generate LO signals by using an efficient LO frequency plan. In the receive path, four separate LNAs are used for each band, and two down-conversion mixers are used, one for the low bands (850/900 MHz) and the other for the high bands (1800/1900 MHz). A receiver baseband circuit is shared for all four bands because all of their channel spaces are the same. In the transmit path, most of the building blocks of the offset PLL, including a TX VCO and IF filters, are integrated. The quad-band GSM transceiver that was implemented in 0.25-/spl mu/m CMOS technology has a size of 3.3/spl times/3.2 mm/sup 2/, including its pad area. From the experimental results, we found that the receiver provides a maximum noise figure of 2.9 dB and a minimum IIP3 of -13.2dBm for the EGSM 900 band. The transmitter shows an rms phase error of 1.4/spl deg/ and meets the GSM spectral mask specification. The prototype chip consumes 56 and 58 mA at 2.8 V in the RX and TX modes, respectively.     

Wavelength and repetition rate tunable optical pulse source using a chirped fiber Bragg grating and a nonlinear optical loop mirror

We experimentally demonstrate a simple and novel scheme for tunable real-repetition-rate multiplication, based on the combined use of fractional Talbot effect in a linearly tunable chirped fiber Bragg grating (FBG) and cross-phase modulation (XPM) effect in a nonlinear optical loop mirror (NOLM). By tuning the group-velocity dispersion of the chirped FBG fabricated with the S-bending method using a uniform FBG, we obtain high quality pulses at pseudorepetition rates of 20/spl sim/50 GHz from an original 8.5-ps 10-GHz soliton pulse train. We subsequently convert this pseudorate multiplication into a real-rate multiplication using XPM effect in an NOLM. A wavelength tuning is also achieved over a /spl sim/15-nm range.     

Fast DCT algorithm with fewer multiplication stages

A novel fast DCT scheme with reduced multiplication stages and fewer additions and multiplications is proposed. The proposed algorithm is structured so that most multiplications tend to be performed at the final stage, which reduces the propagation error that could occur in the fixed-point computation. Minimisation of the multiplication stages can further decrease the error     

Virtual circuit connection method for RSVP multicasting supportingheterogeneous receivers on the ATM network

The authors suggest a novel virtual circuit connection method based on the reverse traversing technique to minimise the waste of network bandwidth resources, when the Internet protocol multicast is interoperated using the resource reservation protocol over an asynchronous transfer mode network. Simulation results show that, as the number of receivers increases, the bandwidth requirements on all links of the network of the proposed scheme become more advantageous than those of other conventional methods     

An ARQ scheme using combined QPSK and BPSK transmissions

We propose a hybrid ARQ scheme which uses QPSK modulation for the first transmission and BPSK modulation for retransmissions. The throughput performance of the proposed ARQ scheme is better that those of ARQ schemes purely using QPSK modulation or purely using BPSK modulation for transmissions. Furthermore, the proposed scheme does not require any operation of error correction as usually required in hybrid ARQ schemes. Therefore, the ARQ scheme proposed in this paper can be easily implemented     

1.04 GBd low EMI digital video interface system using small swingserial link technique

In a high-resolution flat panel system, a conventional interface that directly connects a liquid crystal display (LCD) controller to a flat panel cannot overcome the problems of excess EMI (electromagnetic interference) and power caused by full-swing transmission signals in parallel lines. This paper presents a high-speed digital video interface system implemented with a low-cost standard CMOS (complimentary metal-oxide-semiconductor) technology that can mitigate EMI and power problems in high-resolution flat panel display systems. The combined architecture of the high-speed, small number of parallel lines and low-voltage swing serial interface can support resolutions from VGA (640×480 pixels) up to XGA (1024×768 pixels) with significant power improvement and drastic EMI reduction. To support high-speed, low-voltage swing signaling and overcome channel-to-channel skew problems, a robust data recovery system is required. The proposed digital phase-locked loop enables robust skew-insensitive data recovery of up to 1.04 GBd     

A novel method for elimination of line-current harmonics insingle-stage PFC switching regulators

This paper studies a particular single-stage power-factor-correction (PFC) switching regulator employing a discontinuous-conduction-mode (DCM) boost-input cell and a continuous-current-mode (CCM) forward output cell. Although this single-stage PFC regulator can provide a reasonably high power factor when its PFC stage is operating in discontinuous mode, substantial reduction in line-current harmonics is possible by applying a suitable frequency-modulation scheme. This paper derives a frequency-modulation scheme and proposes a practical implementation using a simple translinear analog circuit. A quantitative analysis on the total harmonic distortion (THD) of the line current when the circuit is subject to a limited range of frequency variations is presented along with some considerations for practical design. Experimental data obtained from a prototype confirms the effectiveness of the proposed frequency-modulation scheme. The proposed analog translinear circuit allows custom integrated circuit implementation, making it a viable low-cost solution to the elimination of line-current harmonics in switching regulators