WCDMA multicarrier receiver for base-station applications

The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF architecture and it is fabricated with a 0.25-/spl mu/m SiGe BiCMOS process to meet the high-performance requirements set by the base-station application. The receiver includes a dual-input low-noise amplifier (LNA), quadrature mixers, a local-oscillator (LO) divider, IIP2 calibration circuits, 10-MHz low-pass filters, and ADC buffers. The receiver noise figures, measured over the downconverted WCDMA channels centered at 2.5-MHz and 7.5-MHz intermediate frequencies, are 3.0 dB and 2.6 dB, respectively. The receiver achieves 47-dB voltage gain and -12-dBm out-of-band IIP3 and consumes 535mW from a 2.5-V supply.     

A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter

In this paper, design and implementation of a multicarrier quadrature amplitude modulation (QAM) modulator for a wideband code division multiple access (WCDMA) base-station with a 14-bit on-chip D/A converter is described. The modulator is capable of modulating four carriers with four independent in phase (I) and quadrature (Q) data streams. The proposed modulator structure consists of an interpolation chain for data streams and four digital frequency synthesizer/modulators, which are based on a coordinate rotation digital computer (CORDIC) vector rotation algorithm. The interpolation chain consists of a root-raised cosine pulse shaping filter and three half-band filters for image filtering. The modulated carriers are combined to form a multicarrier WCDMA signal. The SINC-attenuation effect of a digital/analog (D/A) converter is canceled by an inverse-SINC predistortion filter. The multicarrier signal is converted to the analog domain with a 14-bit current steering D/A converter, which is integrated on the same silicon chip. The modulator is implemented with a 0.35-mum BiCMOS process with CMOS transistors only     

A 14b 100-MS/s Time-Interleaved A/D Converter

This article presents a 14-bit, 100-MS/s time-interleaved pipeline ADC, which samples input signal from 210-MHz IF-band. Digital self-calibration is employed to compensate gain mismatch and offset between time-interleaved channels as well as mismatches arise from a single ADC channel. A timing skew-insensitive parallel S/H circuit is utilized in order to avoid timing skew between parallel ADC channels. The ADC, fabricated in a 0.35-μm BiCMOS (SiGe) takes an area of 10.2 mm², reaches an ENOB of 11.4 bits with a 79.9-dB SFDR at 192.5-MHz input and draws 1.4 W from a 3.0-V supply.     

A direct digital synthesizer with an on-chip D/A-converter

A direct digital synthesizer (DDS) with an on-chip D/A converter is designed and processed in a 0.8 μm BiCMOS. The on-chip D/A converter avoids delays and line loading caused by interchip connections. At the 150 MHz clock frequency, the spurious free dynamic range (SFDR) is better than 60 dBc at low synthesized frequencies, decreasing to 52 dBc worst case at high synthesized frequencies in the output frequency band (0-75 MHz). The DDS covers a bandwidth from DC to 75 MHz in steps of 0.0349 Hz with the frequency switching speed of 140 ns. The chip has a complexity of 19100 transistors with a die/core area of 12.2/3.9 mm². The power dissipation is 0.6 W at 150 MHz at 5 V. The maximum operating clock frequency of the chip is 170 MHz     

Template Design for Cellular Nonlinear Networks With 1-Bit Weights

In this paper, we show how a cellular nonlinear network with 1-bit weight programmability can be used for processing black and white image data. When using such a binary-programmable network, some templates need to be processed algorithmically, in other words, divided into subtasks that are processed consecutively. We classify templates into groups based on their properties and give guidelines as to how the division into subtasks (when applicable) is performed. A large collection of templates suitable for the proposed model is shown. We also describe one possible cell structure that realizes the binary-programmable model. The cell is modeled with Matlab and selected template simulations are shown.     

Environmental protection of inkjet-printed Ag conductors

Electrically conductive silver nanoparticle ink patterns were fabricated using the inkjet printing method. Two different polymer films were used as the substrate materials. The patterns were exposed to humidity and salt fog and the electrical performance (sheet resistance and RF performance) as well as mechanical endurance (adhesion) were measured before and after the environmental tests. The electrical properties of the printed structures remained good in all the measurable samples. The adhesion between the ink and a substrate material appeared to be a greater challenge in harsh environments. Protection capabilities of one dip coated and one hot laminated barrier materials were evaluated during the environmental tests. The results showed that there is a need for environmental protection in printed electronics. Especially the laminated barrier films can offer a potential solution for shielding printed electronics in harsh environments as they can provide good mechanical protection, and can easily be integrated in roll-to-roll process.     

Reducing the crest factor of a CDMA downlink signal by addingunused channelization codes

In a CDMA system the downlink signal typically has a high peak-to-average ratio (crest factor). This sets strict requirements for the linearity of the power amplifier, which leads to poor efficiency and high costs. This letter discusses a method for reducing the crest factor based on the addition of a signal which is orthogonal to all the active channel codes. Therefore, in an ideal case, no error is introduced at the receiver     

Fully differential switched opamp with enhanced common modefeedback

A switched op amp with a fast common mode feedback (CMFB) circuit is presented. The proposed fully differential two stage amplifier needs CMFB only for the second stage, and thus a fast and simple passive CMFB circuit may be used. The amplifier is capable of 1 V operation and has no limitation on the maximum supply voltage     

A computational study of the adsorption of small Ag and Au nanoclusters on graphite

The adsorption of silver and gold atoms, and M2, M6, and M13 (M=Ag or Au) clusters on the (0001) graphite surface has been investigated computationally using the density functional theory (DFT) with periodic boundary conditions and plane wave basis functions. The surface has been modeled as a single carbon sheet. The role of dispersion forces has been studied with an empirical classical model. The results show that the clusters avoid hollow sites on the graphite surface, and that the metal atoms favor atop and bond sites. Large structural changes are observed in octahedral M6 and icosahedral M13 clusters on the graphite surface when compared with gas-phase geometries. The results also indicate that if accurate results are required, the dispersion forces between metal and carbon atoms should be included in the studied systems.     

An analog drive loop for a capacitive MEMS gyroscope

The linear model and the design of an analog drive loop for the drive (primary) resonator in a capacitive gyroscope are presented. Four different types of gain control topologies are compared and analyzed with both P- and PI-type controllers. The simple model proposed in the paper allows the small signal properties of the loop to be predicted. The theoretical models based on the small signal analysis are compared to the simulated and measured results. A proportional amplitude controller, together with the rest of the drive loop, is implemented using a high-voltage 0.35-μm CMOS technology and a nominal supply of 3 V. Clock generation using a PLL and the drive loop signal as the reference are also discussed in the paper.