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131.
Byeong Gi Lee Seok Chang Kim 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1995,83(10):1399-1428
This paper discusses recent advances in the theory and applications of scrambling techniques for digital lightwave transmission. It introduces the theories of sequence space and shift register generator (SRG) space which enable systematic analysis and mathematical manipulation of the behavior of sequences in general and the related SRG's. It discusses the behavior and realization of frame synchronous scrambling (FSS) and distributed sample scrambling (DSS) with emphasis on parallel sequences and the related parallel SRG's (PSRG). In addition, it describes self synchronous scrambling (SSS). Then the paper applies the theories to today's lightwave transmission systems by demonstrating practical parallel designs of FSS for SDH/SONET transmission, DSS for cell-based ATM transmission, and SSS for SDH-based ATM transmission. It finally considers how DSS can be used for scrambling of mixed isochronous and nonisochronous data in future high-speed data networks. The paper employs various new concepts and terminology, such as PSRG engine, generating vector discrimination matrix, (M,N) PSRG, sampling vector, correction vector, correction matrix, predictable scrambling concurrent sampling, and immediate correction 相似文献
132.
Yoon-Ha Jeong Seong-Kue Jo Bong-Hoon Lee Sugano T. 《Electron Device Letters, IEEE》1995,16(3):109-111
High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P3N5 film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 104 seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm 2/V·s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6×1014/cm2 eV has been attained 相似文献
133.
A simple amplitude shift keying (ASK) optical link is demonstrated by using a low-cost self-pulsating laser diode and an envelope detector for a low-cost broadband local area network. A link sensitivity of -22 dBm was achieved at 200 Mbit/s. Because the self-pulsation frequency can be tuned by the bias current, frequency division multiplexing can be simply implemented for multiuser applications 相似文献
134.
Several distributed power control algorithms that can achieve carrier-to-interference ratio (CIR) balancing with probability one have been proposed previously for cellular mobile systems. In these algorithms, only local information is used to adjust transmitting power. However, a normalization procedure is required in each iteration to determine transmitting power and, thus, these algorithms are not fully distributed. In this paper, we present a distributed power control algorithm which does not need the normalization procedure. We show that the proposed algorithm can achieve CIR balancing with probability one. Moreover, numerical results reveal our proposed scheme performs better than the algorithm presented in Grandhi et al. [1994]. The excellent performance and the fully distributed property make our proposed algorithm a good choice for cellular mobile systems 相似文献
135.
Kim S. Jeong S. Lee Y.T. Kim D.-H. Lim J.-S. Seo K.-S. Nam S. 《Electronics letters》2002,38(13):622-623
A new ultra-wideband, low-loss and small-size coplanar waveguide (CPW) to coplanar strip (CPS) transition which can be used from DC to 110 GHz is presented. The proposed transition connects CPW with CPS by the reformed air-bridge. Two ground planes of CPW are tied at their ends by a line and the centre of the line is connected to the ground strip of CPS by another line. Owing to the symmetry of the proposed structure, the currents of two ground planes of CPW are combined with the same phase and transferred to the ground strip of CPS. With height of 3 μm, the signal line of CPW passes over two connecting lines and is connected to the signal strip of CPS. For the back-to-back transition structure, insertion loss <1 dB and return loss >15 dB are obtained from 0.5 to 110 GHz 相似文献
136.
Xiang Lu S. Sundar Kumar Iyer Jin Lee Brian Doyle Zhineng Fan Paul K. Chu Chenming Hu Nathan W. Cheung 《Journal of Electronic Materials》1998,27(9):1059-1066
We have demonstrated feasibility to form silicon-on-insulator (SOI) substrates using plasma immersion ion implantation (PIII)
for both separation by implantation of oxygen and ion-cut. This high throughput technique can substantially lower the high
cost of SOI substrates due to the simpler implanter design as well as ease of maintenance. For separation by plasma implantation
of oxygen wafers, secondary ion mass spectrometry analysis and cross-sectional transmission electron micrographs show continuous
buried oxide formation under a single-crystal silicon overlayer with sharp Si/SiO2 interfaces after oxygen plasma implantation and high-temperature (1300°C) annealing. Ion-cut SOI wafer fabrication technique
is implemented for the first time using PIII. The hydrogen plasma can be optimized so that only one ion species is dominant
in concentration and there are minimal effects by other residual ions on the ion-cut process. The physical mechanism of hydrogen
induced silicon surface layer cleavage has been investigated. An ideal gas law model of the microcavity internal pressure
combined with a two-dimensional finite element fracture mechanics model is used to approximate the fracture driving force
which is sufficient to overcome the silicon fracture resistance. 相似文献
137.
Chang-Hsing Lee Ling-Hwei Chen 《IEEE transactions on image processing》1997,6(11):1587-1591
In this correspondence, a fast approach to motion estimation is presented. The algorithm uses the block sum pyramid to eliminate unnecessary search positions. It first constructs the sum pyramid structure of a block. Successive elimination is then performed hierarchically from the top level to the bottom level of the pyramid. Many search positions can be skipped from being considered as the best motion vector and, thus, the search complexity can be reduced. The algorithm can achieve the same estimation accuracy as the full search block matching algorithm with much less computation time. 相似文献
138.
Parallel BIST architecture for CAMs 总被引:1,自引:0,他引:1
Yong-Seok Kang Jong-Cheol Lee Sungho Kang 《Electronics letters》1997,33(1):30-31
A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved 相似文献
139.
The effect of DC flux on the core loss is examined for the practical range of power and frequency. Relevant core loss equations are derived and applied to an optimization algorithm to determine the minimum core loss at a given ratio of s (DC flux density to AC peak flux density). It has been found that the curves of hysteresis loss density versus the ratio of s exhibit a peak at a critical ratio. Below or above this critical ratio, the loss density decreases drastically. On the other hand, the curves of eddy-current loss density versus the ratio of s exhibits a minimum point at a critical ratio. Below or above this critical ratio, the loss density increases gradually 相似文献
140.
The layout problem of gate matrices and one-dimensional logic arrays is composed of two major tasks: to find a permutation of gates which minimises the number of tracks required and to layout/pack gates based on the ordering. A parallel algorithm is presented which can pack n gates within O(1) time, whereas the conventional near-optimum algorithm needs O(n/sup 2/) time. The simulation results show that the increase of the problem size does not degrade the solution quality.<> 相似文献