Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers

A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V//spl mu/s for a load capacitance of 1 nF almost independently of static currents as low as 1 /spl mu/A, this buffer amplifier is promising for column driver ICs of flat panel displays that require low static power consumption, high current driving capabilities, and small silicon areas.     

Photo-bleaching induced electro-optic polymer modulators with dual driving electrodes operating at 1.55 /spl mu/m wavelength

Electro-optic (EO) polymeric Mach-Zehnder (MZ) modulators with photo-bleaching (PB) induced waveguides and dual driving electrodes operating at 1.55 /spl mu/m wavelength have been demonstrated. The half-wave voltage of the integrated polymeric modulator was 4.5 V in a push-pull configuration with a 1.5 cm interaction length. The extinction ratio was greater than 20 dB, and the fibre-to-fibre insertion loss was 8 dB for the TM polarisation. The achieved fibre-to-fibre insertion loss and driving voltage are the best, to the authors knowledge, in the reported PB induced MZ EO polymeric modulators.     

A One‐Kilobit PQR‐CMOS Smart Pixel Array

The photonic quantum ring (PQR) laser is a three dimensional whispering gallery (WG) mode laser and has anomalous quantum wire properties, such as microampere to nanoampere range threshold currents and √T‐dependent thermal red shifts. We observed uniform bottom emissions from a 1‐kb smart pixel chip of a 32×32 InGaAs PQR laser array flip‐chip bonded to a 0.35 µm CMOS‐based PQR laser driver. The PQR‐CMOS smart pixel array, now operating at 30 MHz, will be improved to the GHz frequency range through device and circuit optimization.     

A graphic approach to performance analysis of multistage linear interference canceller in long-code CDMA systems

The signal-to-interference-plus-noise-ratio performance of the multistage linear parallel and successive interference cancellers (LPIC and LSIC) in a long-code code-division multiple-access system is analyzed using a graphical approach. The decision statistic is modeled as a Gaussian random variable, whose mean and variance can be expressed as functions of moments of R for the LPIC and L for the LSIC, respectively, where R is the correlation matrix of signature sequences and L is the strict lower triangular part of R. Since the complexity of calculating these moments increases rapidly with the growth of the stage index, a graphical representation of moments is developed to facilitate the computation. Propositions are presented to relate the moment calculation problem to several well-known problems in graph theory, i.e., the coloring, the graph decomposition, the biconnected component finding, and the Euler tour problems. It is shown that the derived analytic results match well with simulation results.     

Detection of Target Embedded in Sea Clutter by Means of Millimeter Wave Radar

Sea clutter was measured using a millimeter wave radar with a frequency of 34.86GHz and pulse length of 30ns. A car carrier ship target was embedded in sea clutter. It has been discovered that target pulse-to-pulse fluctuations obey a Weibull distribution and sea clutter obey a Rayleigh distribution. We obtained target to clutter ratio improvement of 23.8dB by applying the cell average LOG/CFAR techniques. The computer simulation has been made to evaluate the detection probability and the false alarm probability. The simulation result was in good agreement with the observed data.     

On-line dead-time compensation method using disturbance observer

A new on-line dead-time compensation method for a permanent magnet (PM) synchronous motor drive is proposed. Using a simple disturbance observer without any additional circuit and off-line experimental measurement, disturbance voltages in the rotor reference dq frame caused by the dead time and nonideal switching characteristics of power devices are estimated in an on-line manner and fed to voltage references in order to compensate the dead-time effects. The proposed method is applied to a PM synchronous motor drive system and implemented by using software of a digital signal processor (DSP) TMS320C31. Simulations and experiments are carried out for this system and the results well demonstrate the effectiveness of the proposed method.     

Monolithic SiGe Up‐/Down‐Conversion Mixers with Active Baluns

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on‐chip 1 to 6 GHz up‐conversion and 1 to 8 GHz down‐conversion mixers using a 0.8 µm SiGe hetero‐junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up‐conversion mixer was implemented on‐chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up‐conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down‐conversion mixer was implemented on‐chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down‐conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.     

K- and Q-bands CMOS frequency sources with X-band quadrature VCO

Fully integrated 10-, 20-, and 40-GHz frequency sources are presented, which are implemented with a 0.18-/spl mu/m CMOS process. A 10-GHz quadrature voltage-controlled oscillator (QVCO) is designed to have output with a low dc level, which can be effectively followed by a frequency multiplier. The proposed multipliers generate signals of 20 and 40 GHz using the harmonics of the QVCO. To have more harmonic power, a frequency doubler with pinchoff clipping is used without any buffers or dc-level shifters. The QVCO has a low phase noise of -118.67 dBc/Hz at a 1-MHz offset frequency with a 1.8-V power supply. The transistor size effect on phase noise is investigated. The frequency doubler has a low phase noise of -111.67 dBc/Hz at a 1-MHz offset frequency is measured, which is 7 dB higher than a phase noise of the QVCO. The doubler can be tuned between 19.8-22 GHz and the output is -6.83 dBm. A fourth-order frequency multiplier, which is used to obtain 40-GHz outputs, shows a phase noise of -102.0 dBc/Hz at 1-MHz offset frequency with the output power of -18.0 dBm. A large tuning range of 39.3-43.67 GHz (10%) is observed.     

Computational Implementation of Asymmetric Integral Imaging by Use of Two Crossed Lenticular Sheets

We propose an asymmetric integral imaging method to adjust the resolution and depth of a three‐dimensional image. Our method is obtained by use of two lenticular sheets with different pitches fabricated under the same F/#. The asymmetric integral imaging is the generalized version of integral imaging, including both conventional integral imaging and one‐dimensional integral imaging. We present experimental results to test and verify the performance of our method computationally.     

Hierarchical classifier design in high-dimensional numerous classcases

In applying pattern recognition methods in remote sensing problems, an inherent limitation is that there is almost always only a small number of training samples with which to design the classifier. A hybrid decision tree classifier design procedure that produces efficient and accurate classifiers for this situation is proposed. In doing so, several key questions are addressed, among them the question of the feature extraction techniques to be used and the mathematical relationship between sample size, dimensionality, and risk value. Empirical tests comparing the hybrid design classifier with a conventional single layered one are presented. They suggest that the hybrid design produces higher accuracy with fewer features. The need for fewer features is an important advantage, because it reflects favorably on both the size of the training set needed and the amount of computation time that will be needed in analysis