多带抗噪声语音识别算法研究

根据Flether等人的研究,基于感知独立性假设的子带识别方法被用于抗噪声鲁棒语音识别。本文拓展子带方法,采用基于噪声污染假定的多带框架来减少噪声影响。论文不仅从理论上分析了噪声污染假定多带框架在识别性能上的潜在优势,而且提出了多带环境下的鲁棒语音识别算法。研究表明：多带框架不仅回避了独立感知假设要求,而且与子带方法相比,多带方法能更好的减少噪声影响,提高系统识别性能。     

电调整微蚀刻

评述了采用电调整微蚀刻试验表明,它适用于各种各样的线宽和间距的精细导线的制造。比起常规喷射蚀刻工艺来,其侧蚀小、蚀刻因子和tanθ高的效果。     

一种零知识证明协议的安全分析与改进

论文指出了文献[1]中的零知识证明协议在公钥参数选取上的安全漏洞,并从求解离散对数的角度进行了分析证明。然后吸取了DSA数字签名算法中安全密钥选取高效简单的优点,提出了一种比Schnorr身份识别方案快1／3的简单、安全、高效的零知识证明身份识别方案。     

个性化公开密钥系统的设计

论文提出利用用户提供的个性化信息来随机产生关联大素数,保证了素数选取的随机化、个性化,提高了RSA算法的安全性。     

基于服务器端会话追踪的Web查询服务的研究

在探讨了Web查询服务的典型模型后,论文阐述了服务器端会话追踪机制的实现方式,设计了基于服务器端会话追踪的Web查询服务的典型解决方案。该设计方案可以较为安全地保存和维护客户的上下文信息,可靠地跟踪用户查询所处的状态,有效地实现有状态的Web查询服务。     

等离子体刻蚀工艺控制模型分析

讨论了主因素分析法以及神经网络法在等离子体刻蚀工艺中的应用.结果表明主元素分析法可以实现对数据的压缩,而神经网络算法则显示出比传统的统计过程控制算法更好的准确性.     

电信企业信息化统一模型构建策略

电信企业信息化的实质就是赋予电信企业精细化的企业资源整合能力，本以此认识为出发点，通过定义基本的信息化业务元素，需求参数和基本信息处理机制，构建出带有行业共性的电信企业信息化统一模型，该模型针对目前电信企业信息化中常见的和潜在的问题提供了有效的解决措施。     

DSP--数字化时代的基因芯片

DSP是当今发展最为迅速的和最有发展前景的技术之一。与普通CPU和MCU相比 ,DSP在数字信号处理方面有着无可比拟的优势 ,特别适合网络、通信、控制等需要进行大量数字信号处理的应用场合。今天DSP已经成为通信、计算机、网络、工业控制以及家用电器等电子产品中不可或缺的基础器件 ,DSP在通信、计算机、网络、工业控制以及消费类电子产品等领域有着非常广泛的应用 ,本文阐述了DSP的特点、应用和市场以及DSP技术的发展前景。     

Study of Disk-Loaded Waveguide Filled with Plasma

Recently disk-loaded waveguide has been widely used in high-power traveling wave tubes (HPTWT). It has been shown in many experiments that the interaction efficiency and output power can be increased greatly by injecting plasma into the vacuum microwave device. Using field analysis, the dispersion characteristics and the interaction impedance of the disk-loaded waveguide filled with plasma are analyzed in a strong longitudinal magnetic field. In conclusion, the frequency of the TM₀₁ mode increases as the density of the plasma increases. It also can be found when the plasma density increases to a large scale, the TM₀₁ mode of the disk-loaded waveguide overlaps the TG mode, these two modes couple each other and form the new hybrid modes.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported