A New Hand-Held Microsystem Architecture for Biological Analysis

This paper presents a hand-held microsystem based on new fully integrated magnetoresistive biochips for biomolecular recognition (DNA hybridization, antibody antigen interaction, etc.). Magnetoresistive chip surfaces are chemically treated, enabling the immobilization of probe biomolecules such as DNA or antibodies. Fluid handling is also integrated in the biochip. The proposed microsystem not only integrates the biochip, which is an array of 16times16 magnetoresistive sensors, but it also provides all the electronic circuitry for addressing and reading out each transducer. The proposed architecture and circuits were specifically designed for achieving a compact, programmable and portable microsystem. The microsystem also integrates a hand-held analyzer connected through a wireless channel. A prototype of the system was already developed and detection of magnetic nanoparticles was obtained. This indicates that the system may be used for magnetic label based bioassays     

WiFi access point pricing as a dynamic game

We study the economic interests of a wireless access point owner and his paying client, and model their interaction as a dynamic game. The key feature of this game is that the players have asymmetric information - the client knows more than the access provider. We find that if a client has a "web browser" utility function (a temporal utility function that grows linearly), it is a Nash equilibrium for the provider to charge the client a constant price per unit time. On the other hand, if the client has a "file transferor" utility function (a utility function that is a step function), the client would be unwilling to pay until the final time slot of the file transfer. We also study an expanded game where an access point sells to a reseller,which in turn sells to a mobile client and show that if the client has a web browser utility function, that constant price is a Nash equilibrium of the three player game. Finally, we study a two player game in which the access point does not know whether he faces a web browser or file transferor type client, and show conditions for which it is not a Nash equilibrium for the access point to maintain a constant price.     

Operating Penalties in Single-Fiber Operation 10-Gb/s, 1024-Way Split, 110-km Long-Reach Optical Access Networks

We report for the first time optical signal-to-noise penalties which lead to performance degradations in single-fiber long-reach optical access networks when compared to identical dual-fiber systems. A simplified architecture, with reduced optical amplifier count compared to previous work, for single-fiber operation of a symmetrical 10-Gb/s, 1024-way split, 110-km long-reach optical access network is presented and demonstrated. In addition, a possible solution to remove the optical signal-to-noise penalty is suggested     

Fast maximum intensity projections of large medical data sets by exploiting hierarchical memory architectures.

Maximum intensity projections (MIPs) are an important visualization technique for angiographic data sets. Efficient data inspection requires frame rates of at least five frames per second at preserved image quality. Despite the advances in computer technology, this task remains a challenge. On the one hand, the sizes of computed tomography and magnetic resonance images are increasing rapidly. On the other hand, rendering algorithms do not automatically benefit from the advances in processor technology, especially for large data sets. This is due to the faster evolving processing power and the slower evolving memory access speed, which is bridged by hierarchical cache memory architectures. In this paper, we investigate memory access optimization methods and use them for generating MIPs on general-purpose central processing units (CPUs) and graphics processing units (GPUs), respectively. These methods can work on any level of the memory hierarchy, and we show that properly combined methods can optimize memory access on multiple levels of the hierarchy at the same time. We present performance measurements to compare different algorithm variants and illustrate the influence of the respective techniques. On current hardware, the efficient handling of the memory hierarchy for CPUs improves the rendering performance by a factor of 3 to 4. On GPUs, we observed that the effect is even larger, especially for large data sets. The methods can easily be adjusted to different hardware specifics, although their impact can vary considerably. They can also be used for other rendering techniques than MIPs, and their use for more general image processing task could be investigated in the future.     

Nonlinearity analysis and optimization of HBTs for optical mixer designs

Two types of photo heterojunction bipolar transistor (HBT) to directly down-convert optical signals to electronic signals have been reported in the literature: a conventional photo-HBT in which light penetrates through the area of the base-collector junction and an HBT where light shines through the base-collector edge for higher conversion efficiency. Although the performance in relation to bias conditions has been published, the detailed analyses for identifying the parameters and bias conditions that provide optimum direct down-conversion have not been examined. This paper provides a full explanation of the operation of the down-conversion for both HBT configurations based on low-frequency analyses. Such information is useful for both understanding the nonlinear mechanisms involved and designing for maximum efficiency. In addition, a new circuit has been developed from the basic HBT down-conversion circuit that provides improved performance.     

Optimal mean-square prediction of the mobile-radio fading envelope

Long-range prediction of the mobile-radio fading envelope is an enabling technology for many fading compensation approaches. Because the fading envelope is well modeled as a bandlimited process, it has special predictability properties. In this paper, we find a linear predictor that is optimal in the mean-square sense when the predictor impulse response is energy constrained. This solution may be used to determine the minimum mean squared error of a prediction based on past values that are corrupted with estimation errors.     

The extended quadratic residue code is the only (48,24,12) self-dual doubly-even code

An extremal self-dual doubly-even binary (n,k,d) code has a minimum weight d=4/spl lfloor/n/24/spl rfloor/+4. Of such codes with length divisible by 24, the Golay code is the only (24,12,8) code, the extended quadratic residue code is the only known (48,24,12) code, and there is no known (72,36,16) code. One may partition the search for a (48,24,12) self-dual doubly-even code into three cases. A previous search assuming one of the cases found only the extended quadratic residue code. We examine the remaining two cases. Separate searches assuming each of the remaining cases found no codes and thus the extended quadratic residue code is the only doubly-even self-dual (48,24,12) code.     

PNNI-based control plane for automatically switched optical networks

Much effort has been spent on the definition of control plane protocols for automatically switched optical networks (ASON). Most of the proposals brought into the standardization for an International Telecommunications Union-Telecommunication Sector, Internet Engineering Task Force, and Optical Internetworking Forum are based on Internet protocol concepts. One such proposal is the generalized multi-protocol label switching (GMPLS), an extension of the MPLS traffic engineering control plane model that includes nonpacket switched technologies (time, wavelength, and fiber switching). Recently, the potential use of private network-network interface (PNNI) in ASONs has been discussed as an alternative proposal by the standardization bodies. The goal of this paper is to appropriately adapt asynchronous transfer mode into an optical PNNI (O-PNNI) protocol that can be used as the control plane of ASONs. The paper also provides a critical viewpoint on the potential usage of either O-PNNI or GMPLS control plane and analyzes the pros and cons of each. The methodology adopted toward devising O-PNNI hinges on reviewing PNNI along with ASON recommendations in order to determine the set of PNNI features that require adaptation. Having identified these features we engineer and present appropriate solutions relating to routing, signaling and addressing aspects.     

Experimental real-time detector of GSM terminals

The authors present an experimental real-time GSM terminal detector, to be installed in a restricted area. The detector triggers terminal signaling, which can be captured.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported