Performance and analysis of saddle point preconditioners for the discrete steady-state Navier-Stokes equations

Summary. We examine the convergence characteristics of iterative methods based on a new preconditioning operator for solving the linear systems arising from discretization and linearization of the steady-state Navier-Stokes equations. With a combination of analytic and empirical results, we study the effects of fundamental parameters on convergence. We demonstrate that the preconditioned problem has an eigenvalue distribution consisting of a tightly clustered set together with a small number of outliers. The structure of these distributions is independent of the discretization mesh size, but the cardinality of the set of outliers increases slowly as the viscosity becomes smaller. These characteristics are directly correlated with the convergence properties of iterative solvers. Received August 5, 2000 / Published online June 20, 2001     

了解高级处理器特点提高编码效率

如今的数字信号处理器(DSP)在性能、外围设备集成、功耗和成本方面都具备很多优势,很多系统设计人员希望在原有系统设计中利用DSP获得比传统处理器更好的效益。但其中一个     

Field dependence of impact ionization coefficients in In/sub 0.53/Ga/sub 0.47/As

Electron and hole ionization coefficients in In/sub 0.53/Ga/sub 0.47/As are deduced from mixed carrier avalanche photomultiplication measurements on a series of p-i-n diode layers, eliminating other effects that can lead to an increase in photocurrent with reverse bias. Low field ionization is observed for electrons but not for holes, resulting in a larger ratio of ionization coefficients, even at moderately high electric fields than previously reported. The measured ionization coefficients are marginally lower than those of GaAs for fields above 250 kVcm/sup -1/, supporting reports of slightly higher avalanche breakdown voltages in In/sub 0.53/Ga/sub 0.47/As than in GaAs p-i-n diodes.     

The G/M/1 queue revisited

The G/M/1 queue is one of the classical models of queueing theory. The goal of this paper is two-fold: (a) To introduce new derivations of some well-known results, and (b) to present some new results for the G/M/1 queue and its variants. In particular, we pay attention to the G/M/1 queue with a set-up time at the start of each busy period, and the G/M/1 queue with exceptional first service. Dedicated to Arie Hordijk on his 65th birthday, in friendship and admiration.     

Deformations of incompressible bodies with free boundaries

Communicated by C. Dafermos     

Poincaré series and holomorphic averaging

Summary We provide an alternate proof of McMullen's theorem on contractive properties of the Poincaré series operator in the special case of the universal covering. This case includes in particular Kra's Theta Conjecture.Oblatum 16-X-1991 & 14-IV-1992First author supported in part by a grant from the National Science Foundation     

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In_0.7Ga_0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system