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21.
Buckminsterfullerene, obtained in good yields at high rates by a suitably designed generator, has been characterized by electron microscopy and in terms of an approximate energy level diagram; C60 undergoes four reversible one-electron reductions giving rise to anionic species and interacts with tetrathiafulvalene to form a charge-transfer complex in the ground state.  相似文献   
22.
We have investigated the nonlinear optical properties of a new class of strained-layer superlattices, the intrinsic Stark effect superlattices (ISES). The superlattices consisted of GaInAs/GaAs grown along the (211) B direction. We observed a shift of the excitonic absorotion to higher energies (blue shift) with increasing intensity of the transmitted beam. The observed optical nonlinearity was about one order of magnitude stronger than the one due to excitonic screening in the (100) oriented reference material. This effect is attributed to the screening of the internal electric fields by photogenerated carriers.  相似文献   
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We report the formation of a new n=3 Ruddlesden-Popper (R-P) layered perovskite oxide, Ca2La2CuTi2O10 (I), in the metathesis reaction between NaLaTiO4 and Ca2CuO2Cl2 (n=1 R-P phases) at 700°C in air. Rietveld refinement of powder XRD data shows that I is isostructural with Sr4Ti3O10 (space group I4/mmm; a=3.8837(5), c=27.727(6) Å), consisting of triple perovskite CuTi2O10 sheets wherein Cu and Ti are ordered at the central and terminal octahedral sites, respectively. Magnetization data provide support for the presence of strong antiferromagnetically coupled CuO2 sheets in the structure. I is metastable decomposing at higher temperatures (∼950°C) to a mixture of perovskite-like CaLa2CuTi2O9 and CaO. Interestingly, the reaction between NaLaTiO4 and Sr2CuO2Cl2 follows a different metathesis route, 2NaLaTiO4+Sr2CuO2Cl2→La2CuO4+2SrTiO3+2NaCl, revealing multiplicity of reaction pathways for solid-state metathesis reactions.  相似文献   
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Product designs for 40-Gb/s applications fabricated from SiGe BiCMOS technologies are now becoming available. In this paper we first briefly discuss heterojunction bipolar transistor (HBT) device operation at high speed, demonstrating that perceived concerns regarding lower BV/sub CEO/ and higher current densities required to operate silicon HBTs at such high speeds do not in actuality limit design or performance. The high-speed portions of the 40-Gb/s system are then addressed individually. We demonstrate the digital capability through a 4: 1 multiplexer and a 1 : 4 demultiplexer running over 50 Gb/s error free at a -3.3-V power supply. We also demonstrate a range of analog elements, including a lumped limiting amplifier which operates with a 35-GHz bandwidth, a transimpedance amplifier with 220-/spl Omega/ gain and 49.1-GHz bandwidth, a 21.5-GHz voltage-controlled oscillator with over -100-dBc/Hz phase noise at 1-MHz offset, and a modulator driver which runs a voltage swing twice the BV/sub CEO/ of the high-speed SiGe HBT. These parts demonstrate substantial results toward product offerings, on each of the critical high-speed elements of the 40-Gb/s system.  相似文献   
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Lead telluride was used as a “captive” source of tellurium (Te) for the n-type doping of gallium antimonide (GaSb) and aluminum antimonide (AlSb)grown by molecular beam epitaxy. Controllable carrier concentrations from 1.2 x 1016 to 1.6 x 1018 cm-3 were obtained. High room-temperature Hall mobilities of 4200 cm2/V · s were measured for the low-doped GaSb samples. In the growth temperature range of interest, doping ef-ficiencies are approximately 50% of those in GaAs. For GaSb, SIMS data show that the Te incorporation decreases significantly at growth temperatures above 500° C. How-ever, in AlSb, there is no significant reduction in the incorporation of Te up to at least 650° C. In contrast, the Te incorporation into AlSb decreases at low temperatures. There is also some evidence of surface segregation in AlSb. Contrary to other doping studies, increasing the Sb : Ga flux ratio was found to reduce the Te incorporation.  相似文献   
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Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 μm and minimum channel length below 0.1 μm. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 μm, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF2 implant were used. Maximum high V DS threshold rolloff was 250 mV at effective channel length of 0.06 μm. For the minimum channel length of 0.1 μm, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively  相似文献   
28.
We present a unified analysis for a class of long-step primal-dual path-following algorithms for semidefinite programming whose search directions are obtained through linearization of the symmetrized equation of the central pathH P (XS) [PXSP –1 + (PXSP –1) T ]/2 = I, introduced by Zhang. At an iterate (X,S), we choose a scaling matrixP from the class of nonsingular matricesP such thatPXSP –1 is symmetric. This class of matrices includes the three well-known choices, namely:P = S 1/2 andP = X –1/2 proposed by Monteiro, and the matrixP corresponding to the Nesterov—Todd direction. We show that within the class of algorithms studied in this paper, the one based on the Nesterov—Todd direction has the lowest possible iteration-complexity bound that can provably be derived from our analysis. More specifically, its iteration-complexity bound is of the same order as that of the corresponding long-step primal-dual path-following algorithm for linear programming introduced by Kojima, Mizuno and Yoshise. © 1998 The Mathematical Programming Society, Inc. Published by Elsevier Science B.V.Corresponding author.This author's research is supported in part by the National Science Foundation under grants INT-9600343 and CCR-9700448 and the Office of Naval Research under grant N00014-94-1-0340.This author's research was supported in part by DOE DE-FG02-93ER25171-A001.  相似文献   
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Transistor design and application considerations for >200-GHz SiGe HBTs   总被引:3,自引:0,他引:3  
SiGe HBT transistors achieving over 200 GHz f/sub T/ and f/sub MAX/ are demonstrated in this paper. Techniques and trends in SiGe HBT design are discussed. Processing techniques available to silicon technologies are utilized to minimize parasitic resistances and capacitances and thereby establish raw speeds exceeding III-V devices despite the higher mobility in those materials. Higher current densities and greater avalanche currents, which are required for establishing such high performance, are discussed as they relate to device self-heating and reliability and the degradation of the devices. Simple circuit results are shown, demonstrating 4.2-ps ring-oscillator delays.  相似文献   
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