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51.
52.
Yang Aiying Wang Ziyu Zhang Zhaoyi Chen Zhangyuan Wu Deming 《电子科学学刊(英文版)》2003,20(6):461-466
A 10Gbit/s recirculating system is configured with Chirped Fiber Bragg Grating (CFBG) for the dispersion compensation. For the first time, the transmission distance in the loop reaches 1000km with bit error rate of 10-9. The effect of the group delay ripple of the fiber grating is also investigated in the recirculating systems, and it is shown that the transmission distance is limited to 4 cycles (4×167.1km ) in the loop with the power penalty fluctuation below 1.0dB. Thus the group delay ripple should be reduced to allow for the wavelength drift of±5GHz. At the end of this letter, the principles are given for designing long haul recirculating systems with dispersion compensation CFBG. 相似文献
53.
High-performance and power-efficient CMOS comparators 总被引:1,自引:0,他引:1
Chung-Hsun Huang Jinn-Shyan Wang 《Solid-State Circuits, IEEE Journal of》2003,38(2):254-262
Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques. 相似文献
54.
The structure, chemical composition, and magnetic properties of electrochemically deposited nanocrystalline Co-Ni-Fe films
were investigated using a number of techniques. A high saturation magnetic induction up to B
s
= 21 kG was attained. An enhancement of the saturation magnetization compared to the ideal anticipated one was revealed,
which correlated with the nonlinear behavior of the structural phase composition and lattice parameters with the change of
the composition.
The text was submitted by the authors in English. 相似文献
55.
Rogin J. Kouchev I. Brenna G. Tschopp D. Qiuting Huang 《Solid-State Circuits, IEEE Journal of》2003,38(12):2239-2248
A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW. 相似文献
56.
Analysis and architecture design of variable block-size motion estimation for H.264/AVC 总被引:1,自引:0,他引:1
Ching-Yeh Chen Shao-Yi Chien Yu-Wen Huang Tung-Chien Chen Tu-Chih Wang Liang-Gee Chen 《IEEE transactions on circuits and systems. I, Regular papers》2006,53(3):578-593
Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory. 相似文献
57.
实验室的质量监督(上) 总被引:4,自引:0,他引:4
质量监督是实验室保持人员能力,进行自我完善,日常渐进的重要手段,是持续改进的重要组成部分,也是实验室管理工作的难点,本文给出质量监督的目的、对象、方法、记录等. 相似文献
58.
59.
Szu-Wei Huang Jenn-Gwo Hwu 《Electron Devices, IEEE Transactions on》2003,50(7):1658-1664
A cost-effective technique was introduced to prepare ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectrics with equivalent oxide thickness (EOT) down to 14 /spl Aring/. Al/sub 2/O/sub 3/ was fabricated by anodic oxidation (anodization) of ultrathin Al films at room temperature in deionized water and then furnace annealed at 650/spl deg/C in N/sub 2/ ambient. Both dc and dac (dc superimposed with ac) anodization techniques were investigated. Effective dielectric constant of k/spl sim/7.5 and leakage current of 2-3 orders of magnitude lower than SiO/sub 2/ are observed. The conduction mechanism in Al/sub 2/O/sub 3/ gate stack is shown to be Fowler-Nordheim (F-N) tunneling. Saturated current behavior in the inversion region of MOS capacitor is observed. It is found that the saturation current is sensitive to interface state capacitance and can be used as an efficient way to evaluate the Al/sub 2/O/sub 3/ gate stack/Si-substrate interfacial property. An optimal process control for preparing Al/sub 2/O/sub 3/ gate dielectrics with minimized interface state capacitance via monitoring the inversion saturation current is demonstrated. 相似文献
60.
分析了设备对PCB电镀过程中孔中镀液更新之影响,为有效地利用设备条件改善孔中镀液的更新提供了一些方法及理论数据。 相似文献