Stability of polymer thin-film transistors based on poly(2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene)

Polymer thin-film transistors (PTFTs) based on poly(2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene) (MEH-PPV) semiconductor are fabricated by spin-coating process and characterized. In the experiments, solution preparation, deposition and device measurements are all performed in air for large-area applications. Hysteresis effect and gate-bias stress effect are observed for the devices at room temperature. The saturation current decreases and the threshold voltage shifts toward the negative direction upon gate-bias stress, but carrier mobility hardly changes. By using quasi-static C-V analysis for MOS capacitor structure, it can be deduced that the origin of threshold-voltage shift upon negative gate-bias stress is predominantly associated with hole trapping within the SiO₂ gate dielectric near the SiO₂/MEH-PPV interface due to hot-carrier emission.     

Allocation heuristics and defragmentation measures for reconfigurable systems management

A novel technique is proposed for the management of a 2D reconfigurable device in order to get true hardware multitasking. We use a Vertex List Set to keep track of the free area boundary. This structure contains the best candidate locations for the task, and several heuristics are proposed to select one of them, based in fragmentation and adjacency. A Look-Ahead heuristic that anticipates the next known event is also proposed. A metric is used to estimate the fragmentation status of the FPGA, based on the number of holes and their shape. Defragmentation measures are taken when needed.