Exhaled breath condensate: Determination of non-volatile compounds and their potential for clinical diagnosis and monitoring. A review

Exhaled breath condensate is a promising, non-invasive, diagnostic sample obtained by condensation of exhaled breath. Starting from a historical perspective of early attempts of breath testing towards the contemporary state-of-the-art breath analysis, this review article focuses mainly on the progress in determination of non-volatile compounds in exhaled breath condensate. The mechanisms by which the aerosols/droplets of non-volatile compounds are formed in the airways are discussed with methodological consequences for sampling. Dilution of respiratory droplets is a major problem for correct clinical interpretation of the measured data and there is an urgent need for standardization of EBC. This applies also for collection instrumentation and therefore various commercial and in-house built devices are described and compared with regard to their design, function and collection parameters. The analytical techniques and methods for determination of non-volatile compounds as potential markers of oxidative stress and lung inflammation are scrutinized with an emphasis on method suitability, sensitivity and appropriateness. The relevance of clinical findings for each group of possible non-volatile markers of selected pulmonary diseases and methodological recommendations with emphasis on interdisciplinary collaboration that is essential for future development into a fully validated clinical diagnostic tool are given.     

On chip novel video streaming system for bi-network multicasting protocols

In the past three decades, tremendous Ethernet-related research has been done, which has led to today's ubiquitous Ethernet technology. On the other hand, with the emergence of new network needs, a new protocol, the IEEE 1394 standard serial bus (or Firewire) was introduced. Firewire is suitable for high-quality audio/video applications which do not perform well in the best-effort-based Ethernet technology. However, since Firewire is a serial bus, it has harsh cable length limitations as compared to Ethernet capabilities.In this paper, we present a novel on-chip system that receives Firewire video and transmits it in multicast mode using Ethernet protocol. A major advantage of this novel system is to utilize the existing Ethernet infrastructure to extend the range of Firewire video streaming to reach remote nodes and make it even accessible to nodes with a single Ethernet interface. This will have tremendous impact on Firewire applications such as deploying Firewire cameras in big-scale security-sensitive buildings or industrial facilities with image-based remote quality control.This novel chip utilizes the concept of Ethernet multicasting transmission mode for video streaming. The proposed chip design converts the IEEE 1394 isochronous traffic to the Ethernet multicast frame format via two off-chip asynchronous write and read buffers.The goal of this research is to design an On Chip Novel Video Streaming System that avoids performance bottlenecks in the software protocol conversion of these two important network protocols. The author decided to study these two networks because of their broad use and cable power provisioning capabilities. The novel system design is implemented using a customized field programmable gate array (FPGA), which enables the integration of various system components on one chip. The designed prototype is studied using both network monitoring tools and analytical techniques, to verify its function and compare it with the existing approaches.Performance measures show that the On Chip Novel Video Streaming System consumes less than 21 mW of power for 100 Mbps and 82 mW of power for 1 Gbps, and utilizes 57% of a Xilinx Spartan 2-100E-6FT256 FPGA resources. Hence, it is possible to incorporate further extensions. Experimental results show that 88% of the network utilization can be achieved, due to the use of the customized, FPGA-based design of bi-network traffic conversion.     

On the Power Allocation and System Capacity of OFDM Systems Using Superimposed Training Schemes

Channel estimation in multipath environments is typically performed using the pilot-symbol-assisted modulation (PSAM) scheme. However, the traditional PSAM scheme requires the use of dedicated pilot subcarriers and therefore leads to a reduction in the bandwidth utilization. Accordingly, this paper investigates a channel-estimation approach for orthogonal frequency-division multiplexing (OFDM) systems using a superimposed training (ST) scheme, in which the pilot symbols are superimposed onto the data streams prior to transmission. By using equally spaced pilot symbols of equal power and assuming that the number of pilots is larger than the channel order, it is shown that the channel-estimation performance is independent of the number of pilots used. The optimal ratio of the pilot symbol power to the total transmission power is analyzed to maximize the lower bound of the channel capacity. Overall, the current results show that the ST-based channel estimation schemes have a slightly poorer performance than the PSAM scheme but yield higher system capacity.     

Design metal-dot based QCA circuits using SPICE model

This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE. In the second half part of the paper, SET and QCA co-design methodology is proposed and SET is used as a readout interface of the QCA cell array. The SET and QCA hybrid circuit is a promising nano-scale solution.     

A monolithic low-power high-voltage driver for bistable LCDs

A complete low-power high-voltage driver for a 80×104 passive-matrix bistable LCD is integrated in a 0.7 μm CMOS smart-power technology. It features 100 V driving capability on all row and column outputs and comprises all necessary digitally programmable high-voltage generators and multiplexers to synthesize the required complex high-voltage waveforms from a 3 V battery. An original level-shifter design for the high-voltage multiplexers and a dedicated architecture for the programmable high-voltage generators yield an extremely low internal power consumption below 10 mW for the entire driver chip.