Reducing leakage power with BTB access prediction

This paper investigates three architectural methods to reduce the leakage power dissipated by the BTB data array. The first method (called here window) periodically places the entire BTB data array into drowsy mode. A drowsy entry is woken up by the first access in the time interval and remains active for the remainder of the interval (window). There is an associated performance loss which is related to the size of the window, since there is a delay when a specific line must be woken up. The second method, awake line buffer (ALB), limits the number of active BTB entries to a predetermined maximum. While this reduces power dissipation it comes with a performance penalty that is relative to the size of the buffer. ALB, however, reduces the power dissipation of the data array more than the window method. The third method, 2-level ALB (2L-ALB), uses a two level buffer with the identical number of combined entries as the previous method. This method exploits the fact that many branches operate numerous times in a fixed sequence. By predicting the next BTB access, 2L-ALB achieves further reduction in leakage power without incurring any further performance loss, compared to the ALB method.     

A low-overhead and reliable switch architecture for Network-on-Chips

This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation of the erroneous flits in NoC is prevented without any need to credit signals and, retransmission buffers. Using an HDL-based NoC simulator, the LRS is compared to two other widely used reliability enhancement methods: the Switch-to-Switch (S2S) and the End-to-End (E2E) methods. The simulation results show that the LRS consumes less power and provides higher performance compared to those of the E2E and S2S methods. More importantly, unlike the E2E and the S2S methods, the LRS has constant overheads, which makes it applicable in all working conditions. To validate the comparison, an analytical performance and reliability model is developed for the LRS, S2S and E2E methods. The results of the model match those obtained from the simulations while the proposed model is significantly faster.     

Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints

3-D (stacked device layers) ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and is promising for heterogeneous integration. In this paper, we concentrate on the configuration number and fixed-outline constraints in the floorplanning for 3-D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3-D IC floorplans. We prove that the number of configuration of 3-D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases. Moreover, we applied the technique of block position enumeration, which have been successfully used in planar fixed-outline floorplanning, to fixed-outline multi-layer floorplanning. The experimental results demonstrate the efficiency and effectiveness of the proposed method.     

Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs

Signal through-the-silicon via (STS-via) planning plays an important role in multi-layer nets which need vertical interconnection between different device layers. Moreover, STS-via can also dissipate heat, which is a much more serious problem in 3D ICs than in 2D ICs. Since the through-the-silicon via is large and can only be inserted into whitespace of the device layer, planning STS-via for thermal optimization may affect the interconnection wire length. Therefore, in order to make STS-via planning more flexible, we integrated STS-via with pin assignment. In this paper, we use min-cost maximum flow algorithm for STS-via planning and pin assignment simultaneously. Experimental results show that our approach can reduce both temperature and wire length effectively with short runtime.     

碳气凝胶及活化碳气凝胶电极材料制备与性能

 以间苯二酚(R)-甲醛(F)为原料,制备了有机气凝胶和碳气凝胶,并对其进行二氧化碳活化。X射线衍射(XRD)测试表明,二氧化碳渗入到碳气凝胶网络结构发生反应,造成(002)峰和(100)峰减弱;扫描电子显微镜(SEM)测试表明,活化没有破坏碳气凝胶的骨架结构,而是增加了大量的nm尺度微孔,从而大大提高了碳气凝胶的比表面积和微孔比例。在1 mol/L KOH电解液中进行了循环伏安和计时电位扫描测试,电极材料电化学性能稳定,具有较好的可逆性,在1 mA/s电流密度下进行充放电测试,得到活化前电极比电容为103 F/g,活化后由于比表面积的增加,比电容达到371 F/g,是一种理想的电化学电极材料。     

Accumulation effect of SiO_2 protective layer on multi-shot laser-induced damage in high-reflectivity HfO_2/SiO_2 coatings

The accumulation effects in high-reflectivity(HR) HfO2/SiO2 coatings under laser irradiation are investigated.The HR HfO2/SiO2 coatings are prepared by electron beam evaporation at 1 064 nm.The laser-induced damage threshold(LIDT) are measured at 1 064 nm and at a pulse duration of 12 ns,in 1-on-1 and S-on-1 modes.Multi-shot LIDT is lower than single-shot LIDT.The laser-induced and native defects play an important role in the multi-shot mode.A correlative theory model based on critical conduction band electron density is constructed to elucidate the experimental phenomena.     

An automated high-level topology generation procedure for continuous-time ΣΔ modulator

This paper presents an automated procedure for generation of high-level topologies for continuous-time ΣΔ modulator system. A functional topology of the system is generated from the given transfer function model of the modulator. Mathematical transformation technique is applied iteratively over the initial topology to generate a functional topology which is optimized for modulator sensitivity, hardware complexity and relative power consumption. This is then implemented using behavioral models of operational transconductance amplifiers and capacitors. The generated high-level topology is ensured to work with reasonable accuracy under non-ideal conditions. The entire procedure has been implemented in Matlab/Simulink environment. Numerical results have been provided to demonstrate the procedure.     

A pre-placement individual net length estimation model and an application for modern circuits

With the advances in integrated circuit (IC) technology, managing the individual and total interconnect is becoming one of the main challenges facing designers. An individual a-priori length estimation model can be a useful tool in helping designers obtain lower net lengths and congestion of interconnect. In this paper, the main characteristics that need to be considered while designing an individual a-priori length estimation technique for today's integrated circuits are discussed. A model that includes some of the most prevalent characteristics is designed and tested using the most current benchmark circuits released by IBM. In addition, one application of the length estimation is proposed in which a predictor-corrector framework for clustering that can be used to improve the results of placement is implemented. This model shows that the corrector step can improve the final placement results by up to 33% for special cases.