Surface-bonded ionic liquid stationary phases in high-performance liquid chromatography—A review

Ionic liquids (ILs) are a class of ionic, nonmolecular solvents which remain in liquid state at temperatures below 100 °C. ILs possess a variety of properties including low to negligible vapor pressure, high thermal stability, miscibility with water or a variety of organic solvents, and variable viscosity. IL-modified silica as novel high-performance liquid chromatography (HPLC) stationary phases have attracted considerable attention for their differential behavior and low free-silanol activity. Indeed, around 21 surface-confined ionic liquids (SCIL) stationary phases have been developed in the last six years. Their chromatographic behavior has been studied, and, despite the presence of a positive charge on the stationary phase, they showed considerable promise for the separation of neutral solutes (not only basic analytes), when operated in reversed phase mode. This aspect points to the potential for truly multimodal stationary phases. This review attempts to summarize the state-of-the-art about SCIL phases including their preparation, chromatographic behavior, and analytical performance.     

Recent developments and applications of screen-printed electrodes in environmental assays—A review

Screen-printed electrodes (SPEs), which are used as economical electrochemical substrates, have gone through significant improvements over the past few decades with respect to both their format and their printing materials. Because of their advantageous material properties, such as disposability, simplicity, and rapid responses, SPEs have been successfully utilised for the rapid in situ analysis of environmental pollutants. This critical review describes the basic fabrication principles, the configuration designs of SPEs and the hybrid analytical techniques based on SPEs. We mainly overview the electrochemical applications of SPEs in environmental analysis over the past 3 years, including the determination of organic compounds, heavy metals and gas pollutants.     

The growth of mixed alkaline-earth fluorides for laser host applications

A comprehensive analysis is implemented concerning the growth, properties, and applications of doped-co-doped single and mixed alkali earth fluoride systems. Calcium-strontium fluoride solid solutions with a Sr content proportion varying widely between 0.007 and 0.675 mol.% are obtained as a batch of axis-symmetrical boules grown by a Bridgman-Stockbarger (BS) method. The crystallization front (CF) can be controlled to retain a convex CF-shape that is favourable for normal growth of single crystals. This achieved using a broad adiabatic furnace zone (AdZ) independently of the boules’ composition. The influence of the thermal field distribution on the CF and the real crystallization rate (CR), which are both critically decisive in controlling crystal quality, were originally assessed using empirically derived formulas. The optical characteristics of the grown boules were monitored by measuring the external transmittance t and calculating the total losses following light irradiation of optical windows that were prepared from sections of the boules that had been cut parallel to one another. The t-measurements were performed by two different techniques and the comparative analysis of the results reliably indicates any inhomogeneity in the grown boules. A simple supercooling criterion proved to closely relate the morphological stability of the CF enabling one to set up the optimum growth conditions. Thus the normal growth criterion outlines the concentration bounds where the isotropic growth mechanism is replaced by cellular anisotropic growth. A procedure has been established for provisioning researchers with optical quality calcium-strontium fluoride crystals with widely varying composition grown under practically identical conditions. As a consequence one can explore possible reasons that can affect the growth mechanism for this or any other systems with a fluoride structure and so provide scope aimed at the future improvement of the crystal quality thereby enlarging the field of mixed fluoride systems’ applications.     

A Novel Dialkylamino-Functionalized Chalcone,DML6, Inhibits Cervical Cancer Cell Proliferation,In Vitro,via Induction of Oxidative Stress,Intrinsic Apoptosis and Mitotic Catastrophe

In this study, we designed, synthesized and evaluated, in vitro, novel chalcone analogs containing dialkylamino pharmacophores in the cervical cancer cell line, OV2008. The compound, DML6 was selective and significantly decreased the proliferation of OV2008 and HeLa cells in sub-micromolar concentrations, compared to prostate, lung, colon, breast or human embryonic kidney cell line (HEK293). DML6, at 5 μM, arrested the OV2008 cells in the G2 phase. Furthermore, DML6, at 5 μM, increased the levels of reactive oxygen species and induced a collapse in the mitochondrial membrane potential, compared to OV2008 cells incubated with a vehicle. DML6, at 5 μM, induced intrinsic apoptosis by significantly (1) increasing the levels of the pro-apoptotic proteins, Bak and Bax, and (2) decreasing the levels of l the anti-apoptotic protein, Bcl-2, compared to cell incubated with a vehicle. Furthermore, DML6, at 5 and 20 μM, induced the cleavage of caspase-9, followed by subsequent cleavage of the executioner caspases, caspase-3 and caspase-7, which produced OV2008 cell death. Overall, our data suggest that DML6 is an apoptosis-inducing compound that should undergo further evaluation as a potential treatment for cervical cancer.     

Towards accelerating irregular EDA applications with GPUs

Recently graphic processing units (GPUs) are rising as a new vehicle for high-performance, general purpose computing. It is attractive to unleash the power of GPU for Electronic Design Automation (EDA) computations to cut the design turn-around time of VLSI systems. EDA algorithms, however, generally depend on irregular data structures such as sparse matrix and graphs, which pose major challenges for efficient GPU implementations. In this paper, we propose high-performance GPU implementations for a set of important irregular EDA computing patterns including sparse matrix, graph algorithms and message-passing algorithms. In the sparse matrix domain, we solve a core problem, sparse-matrix vector product (SMVP). On a wide range of EDA problem instances, our SMVP implementation outperforms all prior work and achieves a speedup up to 50× over the CPU baseline implementation. The GPU based SMVP procedure is applied to successfully accelerate two core EDA computing engines, timing analysis and linear system solution. In the graph algorithm domain, we developed a SMVP based formulation to efficiently solve the breadth-first search (BFS) problem on GPUs. We also developed efficient solutions for two message-passing algorithms, survey propagation (SP) based SAT solution and a register-transfer level (RTL) simulation. Our results prove that GPUs have a strong potential to accelerate EDA computing through designing GPU-friendly algorithms and/or re-organizing computing structures of sequential algorithms.     

Analysis of W-slot loaded patch antenna for dualband operation

In the present paper W-slot loaded single and two dielectric layers microstrip patch antenna has been analysed using equivalent circuit concept. The antenna shows dual resonance. The resonance frequency of single layer patch is found to be 2.91 GHz and 3.88 GHz which increases for two layers dielectric antenna up to 4.17 GHz and 5.78 GHz respectively. The frequency ratio is found to be 1.33 for single layer patch antenna and 1.38 for two layers patch antenna. In general the frequency ratio is found to depend on slot length, slot width and slot angle. The bandwidth of single layer patch antenna is found to be 1.71% and 1.68% for lower and upper resonance frequency while it increases for two layers up to 5.28% and 2.77%. The theoretical results are compared with the simulated results obtained from IE3D and both are in close agreement.     

Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

Constant-time addition with hybrid-redundant numbers: Theory and implementations

Hybrid-redundant number representation has provided a flexible framework for digit-parallel addition in a manner that facilitates area-time tradeoffs for VLSI implementations via arbitrary spacing of redundant digit positions within an otherwise nonredundant representation. We revisit the hybrid redundancy scheme, pointing out limitations such as representational asymmetry, lack of representational closure in certain adder implementations, and difficulties in subtraction and carry acceleration. Given the intuitiveness of the hybrid redundancy concept and its potential for describing practically useful redundant number systems, we are motivated to extend it within the framework of weighted bit-set encodings to circumvent the aforementioned problems. The extension is based mainly on allowing negatively weighted bits (negabits), as well as standard posibits, to appear in nonredundant positions. Our extended hybrid redundancy scheme provides for arbitrary spacing of redundant positions in symmetric digit sets, without any degradation in arithmetic efficiency, while at the same time allowing low-latency subtraction by means of the same circuitry that is used for addition. Finally, we describe how inverted encoding of negabits leads to the exclusive use of unmodified standard full/half-adder, counter, and compressor cells, with no extra inverters, and to the direct applicability of conventional carry acceleration techniques in constant-time addition.