FinFET domino logic with independent gate keepers

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32 nm FinFET technology.     

Performance-driven scheduling of behavioural specifications

Conventional scheduling algorithms usually adjust the clock cycle duration to the execution time of the longest operations. This results in large slack times wasted in those cycles with faster operations. To reduce the wasted times multi-cycle and chaining techniques have been employed. Chaining contributes to reduce the circuit latency if it is applied to the critical path operations, and multi-cycle operators usually result in smaller clock cycles. Both techniques are applied at the operation level, and thus their impact on the circuit performance is bounded by the selected latency. Additionally, they have limited reusability. The design methodology presented in this paper overcomes the limitations of previous techniques to obtain substantially faster circuits. It fragments some of the specification operations into several smaller ones that are handled independently. This way, some operations can begin before their predecessors have finished and can also be executed in several unconsecutive cycles. Furthermore, the fragmentation of operations favours the reusability of hardware resources, leading also to smaller designs.     

Reducing test application time, test data volume and test power through Virtual Chain Partition

A new scan approach is described, named ‘Virtual Chain Partition’ (VCP) architecture, capable of substantially reducing the test application time, test data volume and test power. The VCP architecture maintains the original scan cell order. A simple procedure is proposed, which uses the scan test set generated for the original circuit to determine the maximum reduction in test cycles obtainable with the architecture and to select the most suitable configuration for each circuit. The experiments carried out with the ISCAS 89 benchmarks show that the VCP architecture allows considerable reductions to be achieved both for single and multiple scan chain circuits.     

Thermal aware placement in 3D ICs using quadratic uniformity modeling approach

Three-dimensional (3D) ICs have the potential to reduce the interconnect delay, but thermal problem becomes one of the most serious challenges. In this paper, we proposed an efficient thermal aware 3D placement algorithm,which takes use of quadratic uniformity modeling approach. In this model, cell distribution and thermal dissipation are integrated and formulated as a quadratic function through discrete cosine transformation (DCT) with wirelength optimization. Quadratic programming method is utilized to solve the unified quadratic objective function. We update the unified cell distribution and thermal dissipation with each step of the iterative placement process. Thermal distribution was considered enough during placement process even when a cell was moved. To save time, two fast methods to reflect thermal change were proposed for thermal distribution computation. The experimental results show our thermal aware 3D placement algorithm is efficient with about 3% reduction in average temperature and 15% in max temperature but a little perturbation on wire length.     

A Wireless Sensor Network approach for distributed in-line chemical analysis of water

In this work we propose the implementation of a distributed system based on a Wireless Sensor Network for the control of a chemical analysis system for fresh water. This implementation is presented by describing the nodes that form the distributed system, the communication system by wireless networks, control strategies, and so on.Nitrate, ammonium, and chloride are measured in-line using appropriate ion selective electrodes (ISEs), the results obtained being compared with those provided by the corresponding reference methods. Recovery analyses with ISEs and standard methods, study of interferences, and evaluation of major sensor features have also been carried out.The communication among the nodes that form the distributed system is implemented by means of the utilization of proprietary wireless networks, and secondary data transmission services (GSM or GPRS) provided by a mobile telephone operator. The information is processed, integrated and stored in a control center. These data can be retrieved - through the Internet - so as to know the real-time system status and its evolution.     

CMRR-bandwidth extension technique for CMOS differential amplifiers

An exemplary design demonstrates how to extend the Common-Mode-Rejection-Ratio (CMRR) bandwidth of a CMOS differential amplifier. The design presented uses MOSFETs with a channel length of 180 nm. A novel circuit technique is employed that partially compensates for the output capacitance of the tail current sink, thereby more than quadrupling the CMRR bandwidth in the example considered.     

Use of monoterpenes, 3-carene and 2-carene, as synthons in the stereoselective synthesis of 2,2-dimethyl-1,3-disubstituted cyclopropanes

The current review represents a systematic survey of the use of 2- and 3-carenes in the synthesis of chiral non-racemic organic compounds containing a 2,2-dimethyl-1,3-disubstituted cyclopropane fragment. The synthetic approaches to the cyclopropane derivatives are classified on the basis of the retention of their parent carane bicyclic skeleton in the final product or cleavage of the six-membered ring along the synthetic route.