Robust tracking of moving sound source using scaled unscented particle filter

Tracking an active sound source involves the modeling of non-linear non-Gaussian systems. To address this problem, this paper proposed scaled unscented particle filter (SUPF) algorithm for tracking moving sound source. The particle filter part of the SUPF provides the general probabilistic framework to handle non-linear non-Gaussian systems, and the scaled unscented Kalman filter (SUKF) part of the SUPF generates better proposal distributions by taking into account the most recent observation. Meanwhile, models used in SUPF algorithm were also explored for the sound source motion, observation and the likelihood of the sound source location in the light of the Langevin process. Compared with the conventional PF approach, the simulated results demonstrated that the SUPF algorithm had superior tracking performance.     

Study on fast linear scanning for a new laser scanner

In the field of lidar system design, there is a need for laser scanners that offer fast linear scanning, are small size and have small a rotational inertia moment. Currently, laser scanners do not meet the above needs. A new laser scanner based on two amplified piezoelectric actuators is designed in this paper. The laser scanner has small size, high mechanical resonance frequencies and a small rotational inertia moment. The size of the mirror is 20 mm×15 mm. To achieve fast linear scanning performance, an open-loop controller is designed to compensate the hysteresis behavior and to restrain oscillations that are caused by the mechanical resonances of the scanner's mechanical structure. By comparing measured scanning waveforms, nonlinearities and scan line images between the uncontrolled and controlled scanner, it was found that the scanning linearity of linear scanning was improved The open-loop controlled laser scanner realizes linear scanning at 250 Hz with optical scan angle of ±12 mrad.     

Block flipping and white space distribution for wirelength minimization

Floorplanning plays an important role in the physical design of very large scale integration (VLSI) circuits. Traditional floorplanners use heuristics to optimize a floorplan based on multiple objectives. Besides traditional floorplanning approaches, some post-floorplanning steps can be applied to consider block flipping, pin assignment and white space distribution to optimize the performance. If we can consider the above three optimizations simultaneously as a post-floorplanning step, the total wirelength can be further reduced without modifying the original floorplan topology. Experimental results show that our approach can handle these issues simultaneously and wirelength can be further improved with a small penalty in runtime. Thus, this approach is highly desirable to be incorporated into a floorplanner as a post-processing step for wirelength optimization.     

Implementation of a thermal management unit for canceling temperature-dependent clock skew variations

Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non-negligible impact on delay and reliability is getting significant attention lately.One of the principal factors affecting designs today is timing criticality, which, in today's technologies is mostly determined by wire delays. Clocks, which are the backbone of the interconnect network, are extremely prone to temperature dependent delay variations and need to be designed with extreme care so as to meet accurate timing constraints. Their skew has to be minimized in order to guarantee functionality, albeit in the presence of these process variations.Temperature, on the other hand, is dynamic in nature and its effects hence need run-time monitoring and management. One of the most efficient ways to manage temperature dependent skew is through the use of buffers with dynamically tunable delays. The use of such buffers in the clock distribution network allows modulating the delay on selected branches of the clock network based on a thermal profile, so as to keep the skew within acceptable bounds.A runtime scheme obviously requires an on-line management unit. Our work predominantly focuses on the implementation of one such unit, while studying its impact on design parameters such as area, wire-length and power. Results show negligible a impact (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number) on the design.     

Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application

This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis (STA) technique for designing high-speed low-power SOC applications using 90 nm multi-threshold complementory metal oxide semiconductor (MTCMOS) technology. The cell libraries come in fixed threshold—high V_th for good standby power and low V_th for high speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.     

Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters

Settling behavior of operational amplifiers is of great importance in many applications. In this paper, an efficient methodology for the design of high-speed two-stage operational amplifiers based on settling time is proposed. Concerning the application of the operational amplifier, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. As the effect of transfer function zeros has been taken into account, the proposed methodology becomes more accurate in achieving the desired specifications. Simulation results are presented to show the effectiveness of the methodology.     

Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK

This paper presents a SIMULINK block set for the behavioral modeling and high-level simulation of RF receiver front-ends. The toolbox includes a library with the main RF circuit models that are needed to implement wireless receivers, namely: low noise amplifiers, mixers, oscillators, filters and programmable gain amplifiers. There is also a library including other blocks like the antenna, duplexer filter and switches, required to implement reconfigurable architectures. Behavioral models of building blocks include the main ideal functionality as well as the following non-idealities: thermal noise, characterized by the noise figure and the signal-to-noise ratio, and non-linearity, represented by the input-referred second-order and third-order intercept points, IIP₂ and IIP₃, respectively. In addition to these general parameters, some block-specific errors have also been included, like oscillator phase noise and mixer offset. These models have been incorporated into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of library block elements. This approach reduces the simulation time while keeping high accuracy, which makes the proposed toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As an application of the capabilities of the presented toolbox, a multi-standard direct-conversion receiver intended for 4G telecom systems is modeled and simulated considering the building block requirements for the different standards.