Colloidal Synthesis of Hollow Cobalt Sulfide Nanocrystals

Formation of cobalt sulfide hollow nanocrystals through a mechanism similar to the Kirkendall Effect has been investigated in detail. It is found that performing the reaction at > 120 °C leads to fast formation of a single void inside each shell, whereas at room temperature multiple voids are formed within each shell, which can be attributed to strongly temperature‐dependent diffusivities for vacancies. The void formation process is dominated by outward diffusion of cobalt cations; still, the occurrence of significant inward transport of sulfur anions can be inferred as the final voids are smaller in diameter than the original cobalt nanocrystals. Comparison of volume distributions for initial and final nanostructures indicates excess apparent volume in shells, implying significant porosity and/or a defective structure. Indirect evidence for fracture of shells during growth at lower temperatures was observed in shell‐size statistics and transmission electron microscopy images of as‐grown shells. An idealized model of the diffusional process imposes two minimal requirements on material parameters for shell growth to be obtainable within a specific synthetic system.     

Performance study of iSCSI-based storage subsystems

iISCSI is emerging as an end-to-end protocol for transporting storage I/O block data over IP networks. By exploiting the ubiquitous Internet infrastructure, iSCSI greatly facilitates remote storage, remote backup, and data mirroring. This article evaluates the performance of two typical iSCSI storage subsystems by measuring and analyzing block-level I/O access performance and file-level access performance. In the file-level performance study, we compare file access performance in an NAS scheme with that in an iSCSI-based SAN scheme. Our test results show that Gigabit Ethernet-based iSCSI can reach very high bandwidth, close to that of a direct FC disk access in block I/O access. However, when the iSCSI traverses through longer distance, throughput relies heavily on the available bandwidth between the initiator and the target. On the other hand, the file-level performance shows that iSCSI-based file access (SAN scheme) provides higher performance than using NFS protocol in Linux and SMB protocol in Windows (NAS scheme). However, the advantage of using iSCSI-based file accesses decreases as the file size increases. The obtained experimental results shed some light on the performance of applications based on iSCSI storage.     

Java multimedia telecollaboration

Using Java-based tools in multimedia collaborative environments accessed over the Internet can increase an application's client base. Most operating systems support Java, and its "compile once-run everywhere" architecture is easy to maintain and update. The Java-based tools presented here let users share Internet resources, including resources originally designed for single use.     

Experimental and numerical assessment of gate-lag phenomena in AlGaAs-GaAs heterostructure field-effect transistors (FETs)

Gate-lag effects are characterized in AlGaAs-GaAs heterostructure field-effect transistors (HFETs) by means of measurements and numerical device simulations. Gate lag increasingly affects device switching at increasing ungated recess extension, suggesting that responsible deep levels be located at the ungated, recess surface of the HFET. Gate lag diminishes by making the off-state gate-source voltage less negative and by increasing the drain bias. Increasing the temperature makes the turn-on transient faster at low drain bias, while slightly delaying it at high drain bias. Numerical device simulations accounting for acceptor-like traps at the ungated surface predict gate-lag phenomena in good agreement with experiments, reproducing correctly the observed bias and temperature dependences. Simulations show that surface states behave, during the turn-on transient, as hole traps capturing holes attracted at the ungated surface by the negative trapped charge.     

A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.     

On Faster I DDQ Measurements

The purpose of this paper is to introduce a new I _DDQ measurement technique based on active successive approximations, called ASA-I _DDQ. This technique has unique features facilitating a speed-up in I _DDQ measurement. Experimental results suggest that a significant speed-up factor (up to 4) can be obtained over the QuiC-Mon technique. Such a speed-up is a key element in the replacement of single-threshold I _DDQ testing since it amplifies the effectiveness of post-processing techniques.     

On-demand learning for a wireless campus

The current Internet and wireless networks are harsh environments for transporting high-bandwidth multimedia data. We examine the technical issues involved, and describe an end-to-end solution to support a Web-based learn-on-demand system that operates in a wireless campus environment.     

The extended quadratic residue code is the only (48,24,12) self-dual doubly-even code

An extremal self-dual doubly-even binary (n,k,d) code has a minimum weight d=4/spl lfloor/n/24/spl rfloor/+4. Of such codes with length divisible by 24, the Golay code is the only (24,12,8) code, the extended quadratic residue code is the only known (48,24,12) code, and there is no known (72,36,16) code. One may partition the search for a (48,24,12) self-dual doubly-even code into three cases. A previous search assuming one of the cases found only the extended quadratic residue code. We examine the remaining two cases. Separate searches assuming each of the remaining cases found no codes and thus the extended quadratic residue code is the only doubly-even self-dual (48,24,12) code.