Controlled elements for designing ciphers suitable to efficient VLSI implementation

This work considers the problem of increasing the performance of the ciphers based on Data-Dependent (DD) operations (DDO) for VLSI implementations. New minimum size primitives are proposed to design DDOs. Using advanced DDOs instead of DD permutations (DDP) in the DDP-based iterative ciphers Cobra-H64 and Cobra-H128 the number of rounds has been significantly reduced yielding enhancement of the “performance per cost” value and retaining security at the level of indistinguishability from a random transformation. To obtain further enhancement of this parameter a new crypto-scheme based on the advanced DDOs is proposed. The FPGA implementation of the proposed crypto-scheme achieves higher throughput value and minimizes the allocated resources than the conventional designs. Design of the DDO boxes of different orders is considered and their ASIC implementation is estimated.     

On Faster I DDQ Measurements

The purpose of this paper is to introduce a new I _DDQ measurement technique based on active successive approximations, called ASA-I _DDQ. This technique has unique features facilitating a speed-up in I _DDQ measurement. Experimental results suggest that a significant speed-up factor (up to 4) can be obtained over the QuiC-Mon technique. Such a speed-up is a key element in the replacement of single-threshold I _DDQ testing since it amplifies the effectiveness of post-processing techniques.     

Nonlinearity analysis and optimization of HBTs for optical mixer designs

Two types of photo heterojunction bipolar transistor (HBT) to directly down-convert optical signals to electronic signals have been reported in the literature: a conventional photo-HBT in which light penetrates through the area of the base-collector junction and an HBT where light shines through the base-collector edge for higher conversion efficiency. Although the performance in relation to bias conditions has been published, the detailed analyses for identifying the parameters and bias conditions that provide optimum direct down-conversion have not been examined. This paper provides a full explanation of the operation of the down-conversion for both HBT configurations based on low-frequency analyses. Such information is useful for both understanding the nonlinear mechanisms involved and designing for maximum efficiency. In addition, a new circuit has been developed from the basic HBT down-conversion circuit that provides improved performance.     

On-demand learning for a wireless campus

The current Internet and wireless networks are harsh environments for transporting high-bandwidth multimedia data. We examine the technical issues involved, and describe an end-to-end solution to support a Web-based learn-on-demand system that operates in a wireless campus environment.     

Asymptotic performance of single parity-check product codes

This article investigates the asymptotic performance of single parity-check (SPC) product codes (PCs) from a decoding point of view. Specifically, the probability of bit error is bounded before and after the decoding of each dimension, similar to the analysis of "iterated codes" by Elias (1954). It is shown that the asymptotic probability of bit error can be driven to zero as the number of dimensions, and hence the block length, increases at signal-to-noise ratios (SNRs) within 2 dB of capacity over the additive white Gaussian noise (AWGN) channel.     

Full-diversity, high-rate space-time block codes from division algebras

We present some general techniques for constructing full-rank, minimal-delay, rate at least one space-time block codes (STBCs) over a variety of signal sets for arbitrary number of transmit antennas using commutative division algebras (field extensions) as well as using noncommutative division algebras of the rational field /spl Qopf/ embedded in matrix rings. The first half of the paper deals with constructions using field extensions of /spl Qopf/. Working with cyclotomic field extensions, we construct several families of STBCs over a wide range of signal sets that are of full rank, minimal delay, and rate at least one appropriate for any number of transmit antennas. We study the coding gain and capacity of these codes. Using transcendental extensions we construct arbitrary rate codes that are full rank for arbitrary number of antennas. We also present a method of constructing STBCs using noncyclotomic field extensions. In the later half of the paper, we discuss two ways of embedding noncommutative division algebras into matrices: left regular representation, and representation over maximal cyclic subfields. The 4/spl times/4 real orthogonal design is obtained by the left regular representation of quaternions. Alamouti's (1998) code is just a special case of the construction using representation over maximal cyclic subfields and we observe certain algebraic uniqueness characteristics of it. Also, we discuss a general principle for constructing cyclic division algebras using the nth root of a transcendental element and study the capacity of the STBCs obtained from this construction. Another family of cyclic division algebras discovered by Brauer (1933) is discussed and several examples of STBCs derived from each of these constructions are presented.     

High-efficiency LEDs of 1.6–2.4 µm spectral range for medical diagnostics and environment monitoring

High efficient LED structures covering the spectral range of 1.6–2.4 μm have been developed on the basis of GaSb and its solid solutions. The electroluminescent characteristics and their temperature and current dependences have been studied. The radiative and nonradiative recombination mechanisms and their effect on the quantum efficiency have been investigated. A quantum efficiency of 40–60% has been obtained in the quasi-steady mode at room temperature. A short-pulse optical power of 170 mW was reached. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 37, No. 8, 2003, pp. 996–1009. Original Russian Text Copyright ? 2003 by Stoyanov, Zhurtanov, Astakhova, Imenkov, Yakovlev.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Switched-Current Filters Revisited: Square-Root Domain Sampled-Data Filters

In this brief, the well-known switched-current (SI) filtering technique is revisited using the concept of the square-root domain (SRD) filtering. It is proved that SI filters are a subclass of the SRD filters, where sampled-data signal processing is performed. This is achieved by considering typical lossless and lossy SRD sampled-data integrator configurations, using a set of complementary SRD operators which are based on the quadratic I-V relationship of MOS transistor operated in the saturation. Circuit examples are given, where linear-domain integrator and third-order filter configurations were derived using appropriate SRD sampled-data building blocks