Anharmonic effects in large-amplitude vibrations of metal clusters

Two types of extreme collective motion, large-amplitude many-phonon vibration of the ionic core and rotation of the cluster with high angular momenta, are considered. The interplay between vibration and collective motion towards fission is discussed. A new mechanism of formation and rupture of the neck is proposed which is based on the Franck-Condon principle, and accounts for the interplay between vibration and fission. Under rotation, the change of the shape of the cluster and a phase transition from axially symmetric to triaxial ellipsoid are predicted. For studying the effects, vibrational motion can be induced by laser radiation. Rotational motion may arise in collisions of clusters. Received 26 April 2001 and Received in final form 15 October 2001     

A zero-voltage and zero-current switching three-level DC/DC converter

This paper presents a novel zero-voltage and zero-current switching (ZVZCS) three-level DC/DC converter. This converter overcomes the drawbacks presented by the conventional zero-voltage switching (ZVS) three-level converter, such as high circulating energy, severe parasitic ringing on the rectifier diodes, and limited ZVS load range for the inner switches. The converter presented in this paper uses a phase-shift control with a flying capacitor in the primary side to achieve ZVS for the outer switches. Additionally, the converter uses an auxiliary circuit to reset the primary current during the freewheeling stage to achieve zero-current switching (ZCS) for the inner switches. The principle of operation and the DC characteristics of the new converter are analyzed and verified on a 6 kW, 100 kHz experimental prototype.     

Mechanism analysis of gate-induced drain leakage in off-state n-MOSFET

An analytical expression for both band-to-band and band-trap-band indirect tunnelings is used to study the gate-induced drain leakage (GIDL) current of MOSFETs measured before and after hot-carrier stress. The voltage and temperature dependence of GIDL are characterized. Both results show that interface traps situated near the midgap participate in the conduction of GIDL, and band-trap-band indirect tunneling could be the major mechanism. This is further supported by the fact that the percentage increase in GIDL induced by hot-carrier stress is about the same as the corresponding increase in interface-trap density. On the other hand, under low-field conditions, trap-assisted Poole–Frenkle emission dominates over tunneling for temperatures even well below room temperature.     

A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m (L/sub eff/) NMOS transistors with p/sup +/ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p/sup +/ polysilicon-to-n/sup +/ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.<>     

Multivalued differential equations on closed convex sets in Banach spaces

New derivation results for integrands and multifunctions via the Lipschitzean approximations are obtained. Applications to multivalued differential equations on closed convex sets are presented.     

SAW滤波器简化衍射频响的计算方法

提出了由一个变迹ＩＤＴ叉指换能器和一个均匀ＩＤＴ组成的ＳＡＷ滤波器简化衍射频响的计算方法，即将均匀ＩＤＴ简化成单根指计算其衍射频响。该方法与未简化衍射频响的计算方法相比，计算量大为减小，前者约为后者的（Ｎ为均匀ＩＤＴ的指对数）。并给出了一个实例，用未简化与简化方法分别计算了其衍射频响，结果表明，两者符合得较好。     

Lithographic and pattern transfer of a novel deep-UV photoresist: ARCH2

We have developed a novel chemically amplified deep-UV photoresist called ARCH2. ARCH2 displays a resolution of<0.23μm with a DOF of 1.0μm at 0.25μm. This material also displays superior time delay stability (>8 hours). The post exposure bake (PEB) temperature was varied from 100°C to 120°C and the PEB time was varied from 60s to 180s. This had very little effect on the CD of the resist profiles. Preliminary etching experiments in a conventional reactive ion etcher were then carried out using CF₄ to etch TiN. In these experiments the ARCH2 etched at a similar rate as conventional Novolac.     

Smart sensor interface with A/D conversion and programmablecalibration

In this paper we present a new architecture for a smart sensor interface. It is based on an oversampled A/D converter associated with a small ROM containing calibration coefficients. The nonlinear function desired is obtained by piecewise linear interpolation between the values stored in the ROM, without any additional circuits. This solution has the advantage of high programming flexibility, long-term stability, and low area consumption. Moreover, it is suitable for co-integration with sensors because of its minimum analog content. A prototype was integrated in a CMOS 1.2-μm technology. Simulation and experimental results are reported together with a detailed theoretical analysis and some design guidelines     

Optimization-based placement algorithm for BiCMOS leaf cellgeneration

We present a transistor placement algorithm for the automatic layout synthesis of logic and interface cells comprised of a mixture of MOS and bipolar devices. Our algorithm is applicable to BiCMOS logic cells, ECL logic cells as well as TTL, CMOS and ECL compatible input/output (I/O) cells. The transistor placement problem is transformed into a layout floorplan design problem with a mixture of rigid and flexible modules. A constructive “branch-and-bound” algorithm is used to minimize the area of synthesized circuits subject to pre-placement constraints. Experimental results indicate that the algorithm can produce efficient placements under fixed-height constraints. The design space exploration mechanism can be controlled by the user so as to apportion computing resources judiciously