Java technology comes to real-time applications

The Java language provides many benefits to application developers, including memory access safety, platform portability, and very high levels of productivity. However, some of the very Java language features that bring these benefits, such as the garbage collector, have also made it difficult or impossible to create applications with bounded response time characteristics. Implementations of the real-time specification for Java (RTSJ) are now available that have proven to be capable of supporting all aspects of real-time systems. This paper discusses the principal concepts underlying the RTSJ, use of the RTSJ's features in real-time applications, the most critical considerations that must be addressed by RTSJ-compliant Java virtual machine implementers, and two example RTSJ-compliant application designs that can fully utilize the RTSJ to portably support their performance requirements.     

High-performance self-aligned SiGeC HBT with selectively grown Si/sub 1-x-y/Ge/sub x/C/sub y/ base by UHV/CVD

Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si/sub 1-x-y/Ge/sub x/C/sub y/ layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems.     

High resistivity measurement of SiC wafers using different techniques

To establish fast, nondestructive, and inexpensive methods for resistivity measurements of SiC wafers, different resistivity-measurement techniques were tested for characterization of semi-insulating SiC wafers, namely, the four-point probe method with removable graphite contacts, the van der Pauw method with annealed metal and diffused contacts, the current-voltage (I-V) technique, and the contactless resistivity-measurement method. Comparison of different techniques is presented. The resistivity values of the semi-insulating SiC wafer measured using different techniques agree fairly well. As a result, application of removable graphite contacts is proposed for fast and nondestructive resistivity measurement of SiC wafers using the four-point probe method. High-temperature van der Pauw and room-temperature Hall characterization for the tested semi-insulating SiC wafer was also obtained and reported in this work.     

InGaN microring light-emitting diodes

The fabrication and performance of an InGaN light-emitting diode (LED) array based on a microring device geometry is reported. This design has been adopted in order to increase the surface area for light extraction and to minimize losses due to internal reflections and reabsorption. Electrical characteristics of these devices are similar to those of a conventional large-area LED, while the directed light extraction proves to be superior. In fact, these devices are found to be more efficient when operated at higher currents. This may be attributed to improved heat sinking due to the large surface area to volume ratio. The potential applications of these devices are also discussed.     

Analysis of feedback for higher order polarization-mode dispersion mitigation of NRZ 40-Gb/s optical transmission

First-order polarization-mode dispersion (PMD) compensation by means of a polarization controller and a differential delay line is not sufficient to guarantee error-free transmission for 40-Gb/s channels when higher order effects severely increase signal distortion. Higher order mitigation is possible by cascading more than one first-order block. However, only two-stage or three-stage devices remain simple enough to be actually controlled. The performance of such higher order PMD compensators is evaluated by means of numerical simulations. Two different feedback signals have been used, demonstrating that first-order and higher order PMD distortion of nonreturn-to-zero (NRZ) pulses at 40 Gb/s can be strongly mitigated for instantaneous values of the differential group delay (DGD) up to the bit slot, when the compensator is properly controlled.     

Towards implementation of a nickel silicide process for CMOS technologies

In this paper, we review some of the advantages and disadvantages of nickel silicide as a material for the electrical contacts to the source, drain and gate of current and future CMOS devices. We first present some of the limitations imposed on the current cobalt silicide process because of the constant scaling, of the introduction of new substrate geometries (i.e. thin silicon on insulator) and of the modifications to the substrate material (i.e. SiGe). We then discuss the advantages of NiSi and for each of the CoSi₂ limitations, we point out why Ni is believed to be superior from the point of view of material properties, miscibility of phases and formation mechanisms. Discussion follows on the expected limitations of NiSi and some of the possible solutions to palliate these limitations.     

Construction and qualification of the pre-series MQM superconducting quadrupoles for the LHC insertions

The LHC insertions will be equipped with individually powered MQM superconducting quadrupoles, produced in three versions with magnetic lengths of 2.4 m, 3.4 m, and 4.8 m. The quadrupoles feature a 56 mm aperture coil, designed on the basis of an 8.8 mm wide Rutherford-type NbTi cable for a nominal gradient of 200 T/m at 1.9 K and 5390 A. A total of 96 quadrupoles are in production in Tesla Engineering, UK. In this report we describe the construction of the pre-series MQM quadrupoles and present the results of the qualification tests.     

Search for high-performance probe-fed stacked patches using optimization

High-performance circular probe-fed stacked patch antenna designs are explored through the use of numerical optimization. New trends are sought to aid understanding and to suggest novel solutions. We describe the optimization technique, present a new design trend relating efficiency and bandwidth to the choice of substrate dielectric, and propose and demonstrate a novel, optimized antenna achieving 33% bandwidth whilst maintaining greater than 80% surface wave efficiency.     

End-to-end congestion control schemes: utility functions, random losses and ECN marks

We present a framework for designing end-to-end congestion control schemes in a network where each user may have a different utility function and may experience noncongestion-related losses. We first show that there exists an additive-increase-multiplicative-decrease scheme using only end-to-end measurable losses such that a socially optimal solution can be reached. We incorporate round-trip delay in this model, and show that one can generalize observations regarding TCP-type congestion avoidance to more general window flow control schemes. We then consider explicit congestion notification (ECN) as an alternate mechanism (instead of losses) for signaling congestion and show that ECN marking levels can be designed to nearly eliminate losses in the network by choosing the marking level independently for each node in the network. While the ECN marking level at each node may depend on the number of flows through the node, the appropriate marking level can be estimated using only aggregate flow measurements, i.e., per-flow measurements are not required.