Calibrated Free-Space Microwave Measurements With an Ultrawideband Reflectometer-Antenna System

We present a 3-12 GHz compact mixer-based reflectometer (CMR) and horn antenna system, and demonstrate its use in detecting backscatter signals with a free space calibration procedure. We evaluate the frequency-domain performance of the CMR-antenna system for measuring the complex reflection coefficient of a dielectric slab and compare it with that of a commercial vector network analyzer (VNA)-antenna setup. Time-domain responses are also investigated, and show the effectiveness of this calibration method. This low-cost, compact system eliminates the need for traditional mechanical standards and a VNA, is effective in reducing reflection artifacts, and allows for flexibility in the placement of reference planes; thus it is well suited for array-based imaging applications     

Optimal Block Design for Asynchronous Wake-Up Schedules and Its Applications in Multihop Wireless Networks

In this paper, we consider the problem of designing optimal asynchronous wake-up schedules to facilitate distributed power management and neighbor discovery in multihop wireless networks. We first formulate it as a block design problem and derive the fundamental trade-offs between wake-up latency and the average duty cycle of a node. After the theoretical foundation is laid, we then devise a neighbor discovery and schedule bookkeeping protocol that can operate on the optimal wake-up schedule derived. To demonstrate the usefulness of asynchronous wake-up, we investigate the efficiency of neighbor discovery and the application of on-demand power management, which overlays a desirable communication schedule over the wake-up schedule mandated by the asynchronous wake-up mechanism. Simulation studies demonstrate that the proposed asynchronous wake-up protocol has short discovery time which scales with the density of the network; it can accommodate various traffic characteristics and loads to achieve an energy savings that can be as high as 70 percent, while the packet delivery ratio is comparable to that without power management.     

AIRS/Vis near IR instrument

A component of the Atmospheric Infrared Sounder (AIRS) instrument system is the AIRS/Visible Near InfraRed (Vis/NIR) instrument. With a nadir ground resolution of 2.28 km and four channels, the Vis/NIR instrument provides diagnostic support to the infrared retrievals from the AIRS instrument and several research products, including surface solar flux studies. The AIRS Vis/NIR is composed of three narrowband (channel 1: 0.40-0.44 /spl mu/m; channel 2: 0.58-0.68 /spl mu/m, and channel 3: 0.71-0.92 /spl mu/m) and one broadband (channel 4: 0.49-0.94 /spl mu/m) channel, each a linear detector array of nine pixels. It is calibrated onboard with three tungsten lamps. Vicarious calibrations using ground targets of known reflectance and a cross-calibration with the Moderate Resolution Imaging Spectroradiometer (MODIS) augment the onboard calibration. One of AIRS Vis/NIR's principal supporting functions is the detection of low clouds to flag these conditions for atmospheric temperature retrievals. Once clouds are detected, a cloud height index is obtained based on the ratio (channel 2 - channel 3)/channel 1 that is sensitive to the partitioning of water vapor absorption above and below clouds. The determination of the surface solar radiation flux is principally based on channel 4 broadband measurements and the well-established relationship between top-of-the atmosphere (broadband) radiance and the surface irradiance.     

Experimental and numerical assessment of gate-lag phenomena in AlGaAs-GaAs heterostructure field-effect transistors (FETs)

Gate-lag effects are characterized in AlGaAs-GaAs heterostructure field-effect transistors (HFETs) by means of measurements and numerical device simulations. Gate lag increasingly affects device switching at increasing ungated recess extension, suggesting that responsible deep levels be located at the ungated, recess surface of the HFET. Gate lag diminishes by making the off-state gate-source voltage less negative and by increasing the drain bias. Increasing the temperature makes the turn-on transient faster at low drain bias, while slightly delaying it at high drain bias. Numerical device simulations accounting for acceptor-like traps at the ungated surface predict gate-lag phenomena in good agreement with experiments, reproducing correctly the observed bias and temperature dependences. Simulations show that surface states behave, during the turn-on transient, as hole traps capturing holes attracted at the ungated surface by the negative trapped charge.     

A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.     

On Faster I DDQ Measurements

The purpose of this paper is to introduce a new I _DDQ measurement technique based on active successive approximations, called ASA-I _DDQ. This technique has unique features facilitating a speed-up in I _DDQ measurement. Experimental results suggest that a significant speed-up factor (up to 4) can be obtained over the QuiC-Mon technique. Such a speed-up is a key element in the replacement of single-threshold I _DDQ testing since it amplifies the effectiveness of post-processing techniques.     

On-demand learning for a wireless campus

The current Internet and wireless networks are harsh environments for transporting high-bandwidth multimedia data. We examine the technical issues involved, and describe an end-to-end solution to support a Web-based learn-on-demand system that operates in a wireless campus environment.     

The extended quadratic residue code is the only (48,24,12) self-dual doubly-even code

An extremal self-dual doubly-even binary (n,k,d) code has a minimum weight d=4/spl lfloor/n/24/spl rfloor/+4. Of such codes with length divisible by 24, the Golay code is the only (24,12,8) code, the extended quadratic residue code is the only known (48,24,12) code, and there is no known (72,36,16) code. One may partition the search for a (48,24,12) self-dual doubly-even code into three cases. A previous search assuming one of the cases found only the extended quadratic residue code. We examine the remaining two cases. Separate searches assuming each of the remaining cases found no codes and thus the extended quadratic residue code is the only doubly-even self-dual (48,24,12) code.     

Switched-Current Filters Revisited: Square-Root Domain Sampled-Data Filters

In this brief, the well-known switched-current (SI) filtering technique is revisited using the concept of the square-root domain (SRD) filtering. It is proved that SI filters are a subclass of the SRD filters, where sampled-data signal processing is performed. This is achieved by considering typical lossless and lossy SRD sampled-data integrator configurations, using a set of complementary SRD operators which are based on the quadratic I-V relationship of MOS transistor operated in the saturation. Circuit examples are given, where linear-domain integrator and third-order filter configurations were derived using appropriate SRD sampled-data building blocks