Reliable eye-diagram analysis of data links via device macromodels

This paper addresses the impact of device macromodels on the accuracy of signal integrity and performance predictions for critical digital interconnecting systems. It exploits nonlinear parametric models for both single-ended and differential devices, including the effects of power supply fluctuations and receiver bit detection. The analysis demonstrates that the use of well-designed macromodels dramatically speeds up the simulation as well it preserves timing accuracy even for long bit sequences.     

PowerNap: an efficient power management scheme for mobile devices

We present PowerNap, an OS power management scheme, which can significantly improve the battery life of mobile devices. The key feature of PowerNap is the skipping of the periodic system timer ticks associated with the operating system. On an idle device, this modification increases the time between successive timer interrupts and enables us to put the processor/system into a more efficient low power state. This saves the energy consumed by workless timer interrupts and the excess energy consumed by the processor in less efficient low power states. PowerNap is tightly integrated with the kernel and is designed for optimal control of the latency and energy associated with transitioning in and out of the low power states. We describe an implementation of PowerNap and its impact on system software. Experiments with IBM's WatchPad verify the ability of PowerNap to extend battery life. An analytical model that quantifies the ability of the scheme to reduce power is also presented. The model is in good agreement with experimental results. We apply the model to small form-factor devices which use processors that have a PowerDown state. In such devices, PowerNap may extend battery life by more than 42 percent for small processor workloads and for background power levels below 10 mW.     

The method of double averaging: an approach for modeling power-factor-correction switching converters

This paper describes the modeling of power-factor-correction converters under average-current-mode control, which are widely used in switch-mode power supply applications. The objective is to identify stability boundaries in terms of major circuit parameters for facilitating design of such converters. The approach employs a double averaging procedure, which first applies the usual averaging over the switching period and subsequently applies generalized averaging over the mains period. The resulting model, after two averaging steps and application of a harmonic balance procedure, is nonlinear and capable of describing the low-frequency nonlinear dynamics of the system. The parameter ranges within which stable operation is guaranteed can be accurately and easily found using this model. Experimental measurements are provided for verification of the analytical results.     

Colloidal Synthesis of Hollow Cobalt Sulfide Nanocrystals

Formation of cobalt sulfide hollow nanocrystals through a mechanism similar to the Kirkendall Effect has been investigated in detail. It is found that performing the reaction at > 120 °C leads to fast formation of a single void inside each shell, whereas at room temperature multiple voids are formed within each shell, which can be attributed to strongly temperature‐dependent diffusivities for vacancies. The void formation process is dominated by outward diffusion of cobalt cations; still, the occurrence of significant inward transport of sulfur anions can be inferred as the final voids are smaller in diameter than the original cobalt nanocrystals. Comparison of volume distributions for initial and final nanostructures indicates excess apparent volume in shells, implying significant porosity and/or a defective structure. Indirect evidence for fracture of shells during growth at lower temperatures was observed in shell‐size statistics and transmission electron microscopy images of as‐grown shells. An idealized model of the diffusional process imposes two minimal requirements on material parameters for shell growth to be obtainable within a specific synthetic system.     

Performance study of iSCSI-based storage subsystems

iISCSI is emerging as an end-to-end protocol for transporting storage I/O block data over IP networks. By exploiting the ubiquitous Internet infrastructure, iSCSI greatly facilitates remote storage, remote backup, and data mirroring. This article evaluates the performance of two typical iSCSI storage subsystems by measuring and analyzing block-level I/O access performance and file-level access performance. In the file-level performance study, we compare file access performance in an NAS scheme with that in an iSCSI-based SAN scheme. Our test results show that Gigabit Ethernet-based iSCSI can reach very high bandwidth, close to that of a direct FC disk access in block I/O access. However, when the iSCSI traverses through longer distance, throughput relies heavily on the available bandwidth between the initiator and the target. On the other hand, the file-level performance shows that iSCSI-based file access (SAN scheme) provides higher performance than using NFS protocol in Linux and SMB protocol in Windows (NAS scheme). However, the advantage of using iSCSI-based file accesses decreases as the file size increases. The obtained experimental results shed some light on the performance of applications based on iSCSI storage.     

Java multimedia telecollaboration

Using Java-based tools in multimedia collaborative environments accessed over the Internet can increase an application's client base. Most operating systems support Java, and its "compile once-run everywhere" architecture is easy to maintain and update. The Java-based tools presented here let users share Internet resources, including resources originally designed for single use.     

Experimental and numerical assessment of gate-lag phenomena in AlGaAs-GaAs heterostructure field-effect transistors (FETs)

Gate-lag effects are characterized in AlGaAs-GaAs heterostructure field-effect transistors (HFETs) by means of measurements and numerical device simulations. Gate lag increasingly affects device switching at increasing ungated recess extension, suggesting that responsible deep levels be located at the ungated, recess surface of the HFET. Gate lag diminishes by making the off-state gate-source voltage less negative and by increasing the drain bias. Increasing the temperature makes the turn-on transient faster at low drain bias, while slightly delaying it at high drain bias. Numerical device simulations accounting for acceptor-like traps at the ungated surface predict gate-lag phenomena in good agreement with experiments, reproducing correctly the observed bias and temperature dependences. Simulations show that surface states behave, during the turn-on transient, as hole traps capturing holes attracted at the ungated surface by the negative trapped charge.     

A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.