On the selective counting of third-order products

A practical and efficient method is presented for the counting of third-order products generated by an arbitrary number of carriers with arbitrary power spectral shapes. In particular, three selective counting procedures (i.e. sorting by position, sorting by position and group, and sorting by position, group, and kind) are introduced in a systemic way, based upon a discrete third-order Volterra model. The advantage of the counting algorithm is that (1) the algorithm provides the exact counting of third-order products of all eleven possible groups; (2) the counting process requires only two multiplications for the selective counting of third-order products at each position, and the algorithm, which is thus efficient, can be easily implemented     

Self-aligned offset gated poly-Si TFTs with a floating sub-gate

We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained     

The magnetic entropy changes in Gd1−xBx alloys

A series of Gd_(1−x)B_x alloys have been prepared by arc melting method. After introducing small quantity of B atom in Gd, the Curie temperature of these alloys increase while the magnetic entropy changes are almost same as that of Gd. The refrigerant capacities of these alloys are also greater than that of Gd. These results suggest that Gd_(1−x)B_x alloys may be utilized as refrigerant in household magnetic refrigeration.     

Generation of 0.2-TW 5.5-fs optical pulses at 1 kHz using a differentially pumped hollow-fiber chirped-mirror compressor

Optical pulses with 1.1-mJ energy and 5.5-fs duration have been generated at 1-kHz repetition rate from a chirped pulse amplification Ti:Sapphire laser incorporating a differentially pumped hollow-fiber chirped-mirror compressor. The effects of self-focusing and multi-photon ionization during the beam propagation were minimized by differentially pumping the hollow fiber filled with neon. The spectral broadening at the hollow-fiber compressor was optimized by adjusting gas pressure, laser intensity, and laser chirp, covering from 540 nm to 950 nm. PACS 42.65.Jx; 42.65.Re     

γ-LiAlO2晶体生长、改性和热学性质研究

采用快速提拉法生长出了透明、完整的γ-LiAlO2晶体,但是晶体的高熔点和易挥发性限制了γ-LiAlO2晶体质量.采用气相传输平衡法(vapor transport equilibration technique,VTE)工艺对晶体改性,半高宽(FWHM)值从116.9arcsec降至44.2arcsec,继续升高VTE处理温度至1300℃,FWHM值反而升高至55.2arcsec.快速提拉法生长出来晶体,[100]方向和[001]方向的热膨胀系数分别为17.2398×10-6/K,10.7664×10-6/K.经过三步VTE处理后[100]和[001]方向热膨胀系数降至16.6539×10-6/K和10.1784×10-6/K.     

Design,Implementation, and Validation of KOMPSAT‐2 Software Simulator

In this paper, we present design features, implementation, and validation of a satellite simulator subsystem for the Korea Multi‐Purpose Satellite‐2 (KOMPSAT‐2). The satellite simulator subsystem is implemented on a personal computer to minimize costs and trouble on embedding onboard flight software into the simulator. An object‐oriented design methodology is employed to maximize software reusability. Also, instead of a high‐cost commercial database, XML is used for the manipulation of spacecraft characteristics data, telecommand, telemetry, and simulation data. The KOMPSAT‐2 satellite simulator subsystem is validated by various simulations for autonomous onboard launch and early orbit phase operations, anomaly operation, and science fine mode operation. It is also officially verified by successfully passing various tests such as the satellite simulator subsystem test, mission control element system integration test, interface test, site installation test, and acceptance test.     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.     

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-/spl mu/m CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5/spl times/10/sup -15/ while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.