An Injection-Locked Frequency-Tracking Σ∆ Direct Digital Frequency Synthesizer

A bandpass (BP) sigma-delta modulator (SigmaDeltaM)-based direct digital frequency synthesizer (DDS) architecture is presented. The DDS output is passed through a single-bit, second-order BPSigmaDeltaM, shaping quantization noise out of the signal band. The single-bit BPSigmaDeltaM is then injection locked to an LC-tank oscillator, which provides a tracking BP filter response within its locking range, suppressing the BPSigmaDeltaM out of band quantization noise. The instantaneous digital frequency control word input of the DDS is used to tune the noise shaper center frequency, achieving up to 20% tuning range around the fundamental. The BPSigmaDeltaM-based synthesizer is fabricated in a 0.25-mum digital CMOS process with four layers of metal. With a second-order BP noise shaper and a 44-MHz LC tank oscillator, an SFDR of 73 dB at a 2-MHz bandwidth and phase noise lower than -105 dBc/Hz at a 10-kHz offset is achieved     

Polar SiGe Class E and F Amplifiers Using Switch-Mode Supply Modulation

Two integrated polar supply-modulated class E and F power amplifiers (PAs) in 0.18-mum SiGe BiCMOS process are presented. The amplifiers are used to transmit GSM-EDGE signals with an envelope dynamic range of 11 dB and a frequency range of 880-915 MHz. The amplifiers use switch-mode dc-dc buck converters for supply modulation, where sigma-delta (SigmaDeltaM), delta (DeltaM), and pulsewidth modulation are used to modulate the PA amplitude signal. A framework has been developed for comparing the three switching techniques for EDGE implementation. The measurement results show that DeltaM gives the highest efficiency and lowest adjacent channel power, providing class E and F PA efficiencies of 33% and 31%, respectively, at maximum EDGE output power. The corresponding class E and F linearized amplifiers' output spectra at 400-kHz offset are -54 and -57dBc, respectively     

Invariant approach to optimal investment–consumption problem: the constant elasticity of variance (CEV) model

The optimal investment–consumption problem under the constant elasticity of variance (CEV) model is solved using the invariant approach. Firstly, the invariance criteria for scalar linear second‐order parabolic partial differential equations in two independent variables are reviewed. The criteria is then employed to reduce the CEV model to one of the four Lie canonical forms. It is found that the invariance criteria help in transforming the original equation to the second Lie canonical form and with a proper parameter selection; the required transformation converts the original equation to the first Lie canonical form that is the heat equation. As a consequence, we find some new classes of closed‐form solutions of the CEV model for the case of reduction into heat equation and also into second Lie canonical form. The closed‐form analytical solution of the Cauchy initial value problems for the CEV model under investigation is also obtained. Copyright © 2016 John Wiley & Sons, Ltd.     

Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers

Design and analysis of a Σ∆ modulator with a passive switched capacitor loop filter is presented. Design steps for optimum loop filter design for quantization noise suppression and thermal noise reduction is outlined. Design specifications for sampling clock phase noise, reference buffer and input buffer settling is analyzed. Presented design has a 2nd-order loop filter and uses only metal-metal capacitors and thin oxide digital transistors with no additional components occupying less than 0.1 mm² silicon area in 0.13 μm CMOS digital process. Measurement results show that the ADC achieves 80 dB peak SNR at a 100 kHz integration bandwidth with 1 pJ/sample conversion efficiency. With decimation filter power consumption of 0.22 mW at 104 MHz sampling rate, the ADC consumes only about 1 mA at 1.5 V for each channel.     

模块化基带设计实现低成本可重用无线架构

过去的十年里,无线基站设计者们在努力降低成本、功耗和占板空间方面已经取得了巨大进展。对于这些设计者来说,3G基站开发的目的非常明确,以十分之一的成本实现十倍的带宽。处理基带算法所需的处理能力随着新的无线协议的出现正在不断增加。传统数字信号处理器(DSP)的速度无法实现基带处理,因此需要硬件加速来补充DSP。一个典型架构可能由一系列的数字信号处理器和基带卡上的硬件加速器模块构成,这里需要多通道处理。     

Influence of the Addition of Lauric Acid to Films Made from Gelatin,Triacetin and a Blend of Stearic and Palmitic Acids

Summary: The objective of this research was to verify the influence of adding increasing amounts of lauric acid on the functional properties of homogenized films made from gelatin, triacetin and a blend of palmitic and stearic acids. The films were characterised with respect to their visual aspect, water vapour permeability (WVP), water solubility, mechanical properties (tensile strength and percent elongation), oxygen permeability (O₂P), opacity (OP) and melting and glass transitions temperatures. The films produced were malleable and macroscopically homogeneous. The addition of 1% of lauric acid to the film of gelatin, triacetin and blend of palmitic and stearic acids (5.84 ± 0.31 gmm · m⁻² dkPa) caused a slight decrease in WVP. The additions of 2.5% (5.70 ± 0.76 gmm · m⁻² dkPa), 5% (5.38 ± 0.64 gmm · m⁻² dkPa) and 10% (4.50 ± 0.55 gmm · m⁻² dkPa) of lauric acid were sufficient to make a significant difference in the WVP at the higher levels used. As compared to the gelatin and triacetin film, the addition of lauric acid at all the concentrations studied resulted in a slight increase in the film solubility. The addition of hydrophobic substances to gelatin/triacetin films (15.26 ± 0.28 cm³ · µm · m⁻² dkPa) favoured an increase in O₂P permeability, this effect being greater in the films made from gelatin, triacetin, blend of palmitic and stearic acids and 10% lauric acid (24.48 ± 0.07 cm³ · µm · m⁻² dkPa). The increasing addition of lauric acid significantly reduced the tensile strength and increased elongation of the films composed of gelatin, triacetin and blend that being more evident at the concentrations of 5% (67.58 ± 1.23 MPa and 11.45 ± 0.57%) and 10% (63.50 ± 1.56 MPa and 12.90 ± 0.57%). The addition of 1% (OP, 27%) and 10% (OP, 28%) of lauric acid induced no visible effect on the opacity of the films. The thermogrammes showed three transitions for the gelatin/triacetin/stearic-palmitic blend/1% lauric acid films (−57.42 °C, 23.74 °C and 44.11 °C) and two for the gelatin/triacetin/stearic-palmitic acids blend/10% lauric acid films (−56.22 °C and 17.35 °C). As observed by DSC, the addition of fatty acids resulted in the appearance of more than one melting peak for all films in relation to the gelatin and triacetin film.     

Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25?μm SOS process

This paper presents an analog image recognition system with a novel MESFET device fabricated on a fully depleted (FD) CMOS process. An analog image recognition system with a power consumption of 2.4?mW/cell and a settling time of 6.5???s was designed, fabricated and characterized. A CNN is employed to realize a core cell of the proposed image recognition system. While a CNN benefits from its regular structure, it faces challenges due to its power consumption, speed, and size in their CMOS implementations. SOS MESFETs can deal with the challenges associated with CMOS-based CNNs. Advantages of SOS MESFETs associated with nonlinear signal processing include lower power consumption and higher operating speeds compared to similar geometry MOSFETs carrying the same current. SOS MESFET-based analog image recognition systems were fabricated and the transient response is characterized in both simulation using a TOM3 SPICE model extracted from SOS MESFETs and in experiment using image testing lab equipment. Settling times of 3.5 and 6.5???s for one-by-four and one-by-eight arrays, respectively, were achieved with line recognition template. The corresponding power consumption for the two arrays was 9.6 and 19.2?mW, respectively.     

A Multistage Interleaved Synchronous Buck Converter With Integrated Output Filter in 0.18 μm SiGe Process

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 mum SiGe RF BiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA.