Training and optimization of an artificial neural network controlling a hybrid power filter

A hybrid power compensator (HPC) consisting of a static VAr compensator and a dynamic compensator needs to be optimally controlled during the compensation of nonlinear loads. The HPC must be controlled to meet minimum requirements in terms of power factor and harmonic distortion, while at the same time minimizing its total cost. An artificial neural network (ANN) is used to control the HPC amidst a very dynamic power system environment. The performance of a reference ANN is evaluated while controlling an HPC connected to a typical nonlinear industrial load. The training and performance of the ANN is then optimized in terms of training set size, training set packing and ANN topology and the performance compared to the reference ANN. This paper highlights the importance of optimising the mentioned ANN parameters to achieve optimum ANN training and modeling accuracy. The results obtained reveals that the application of an ANN in controlling an HPC is feasible given that the ANN parameters are chosen appropriately.     

Analytic models for the latency and steady-state throughput of TCP Tahoe, Reno, and SACK

Continuing the process of improvements made to TCP through the addition of new algorithms in Tahoe and Reno, TCP SACK aims to provide robustness to TCP in the presence of multiple losses from the same window. In this paper we present analytic models to estimate the latency and steady-state throughput of TCP Tahoe, Reno, and SACK and validate our models using both simulations and TCP traces collected from the Internet. In addition to being the first models for the latency of finite Tahoe and SACK flows, our model for the latency of TCP Reno gives a more accurate estimation of the transfer times than existing models. The improved accuracy is partly due to a more accurate modeling of the timeouts, evolution of cwnd during slow start and the delayed ACK timer. Our models also show that, under the losses introduced by the droptail queues which dominate most routers in the Internet, current implementations of SACK can fail to provide adequate protection against timeouts and a loss of roughly more than half the packets in a round will lead to timeouts. We also show that with independent losses SACK performs better than Tahoe and Reno and, as losses become correlated, Tahoe can outperform both Reno and SACK.     

Synthesis of ZSM‐5 Films and Monoliths with Bimodal Micro/Mesoscopic Structures

A route to synthesize ZSM‐5 crystals with a bimodal micro/mesoscopic pore system has been developed in this study; the successful incorporation of the mesopores within the ZSM‐5 structure was performed using tetrapropylammonium hydroxide (TPAOH)‐impregnated mesoporous materials containing carbon nanotubes in the pores, which were encapsulated in the ZSM‐5 crystals during a solid rearrangement process within the framework. Such mesoporous ZSM‐5 zeolites can be readily obtained as powders, thin films, or monoliths.     

The First Template‐Free Growth of Crystalline Silicon Microtubes

A simple template‐free high‐temperature evaporation method was developed for the growth of crystalline Si microtubes for the first time. As‐grown Si microtubes were characterized using X‐ray diffraction, scanning electron microscopy, transmission electron microscopy, and room‐temperature photoluminescence. The lengths of the Si tubes can reach several hundreds of micrometers; some of them have lengths on the order of millimeters. Each tube has a uniform outer diameter along its entire length, and the typical outer diameter is ≈ 2–3 μm. Most of the tubes have a wall thickness of ≈ 400–500 nm, though a considerable number of them exhibit a very thin wall thickness of ≈ 50 nm. Room‐temperature photoluminescence measurement shows the as‐synthesized Si microtubes have two strong emission peaks centered at ≈ 589 nm and ≈ 617 nm and a weak emission peak centered at ≈ 455 nm. A possible mechanism for the formation of these Si tubes is proposed. We believe that the present discovery of the crystalline Si microtubes will promote further experimental studies on their physical properties and smart applications.     

Optimal pilot waveform assisted modulation for ultrawideband communications

Ultrawideband (UWB) transmissions induce pronounced frequency-selective fading effects in their multipath propagation. Multipath diversity gains can be collected to enhance performance, provided that the underlying channel can be estimated at the receiver. To this end, we develop a novel pilot waveform assisted modulation (PWAM) scheme that is tailored for UWB communications. We select our PWAM parameters by jointly optimizing channel estimation performance and information rate. The resulting transmitter design maximizes the average capacity, which is shown to be equivalent to minimizing the mean-square channel estimation error, and thereby achieves the Crame/spl acute/r-Rao lower bound. Application of PWAM to practical UWB systems is promising because it entails simple integrate-and-dump operations at the frame rate. Equally important, it offers a flexible UWB channel estimator, capable of striking desirable rate-performance tradeoffs depending on the channel coherence time.     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

Static energy reduction techniques for microprocessor caches

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Near-ML multiuser detection with linear filters and reliability-based processing

The prohibitive - exponential in the number of users - computational complexity of the maximum-likelihood multiuser detector for direct-sequence code-division multiple-access communications has fueled an extensive research effort for the development of low-complexity multiuser detection alternatives. We show that we can efficiently and effectively approach the error rate performance of the optimum multiuser detector as follows. We utilize a multiuser zero-forcing or minimum mean-square error (MMSE) linear filter as a preprocessor and we establish that the output magnitudes, when properly scaled, provide a reliability measure for each user bit decision. Then, we prepare an ordered, reliability-based error search sequence of length linear in the number of users; it returns the most likely user bit vector among all visited options. Numerical and simulation studies for moderately loaded systems that permit exact implementation of the optimum detector indicate that the error rate performance of the optimum and the proposed detector are nearly indistinguishable over the whole predetection. signal-to-noise ratio range of practical interest. Similar studies for higher user loads (that prohibit comparisons with the optimum detector) demonstrate error rate performance gains of orders of magnitude in comparison with straight decorrelating or MMSE multiuser detection.     

The effects of nonlocal impact ionization on the speed of avalanche photodiodes

The nonlocal enhancement in the velocities of charge carriers to ionization is shown to outweigh the opposing effects of dead space, increasing the avalanche speed of short avalanche photodiodes (APDs) over the predictions of a conventional local model which ignores both of these effects. The trends in the measured gain-bandwidth product of two short InAlAs APDs reported in the literature support this result. Relatively large speed benefits are predicted to result from further small reductions in the lengths of short multiplication regions.