A new route for the construction of the AB-ring core of Taxol

A new method for the construction of the AB-ring core of Taxol was developed utilizing a new skeletal transformation protocol as a pivotal step. The acid-catalyzed rearrangement of the cyclopentenone-allene photoadduct gave a bridged seven-membered ketone, which was easily transformed, using the intramolecular Suzuki reaction and the oxidative cleavage of the vicinal diol, to the bicyclic diketone.     

Unique continuation along curves and hypersurfaces for second order anisotropic hyperbolic systems with real analytic coefficients

In this paper we prove the following kind of unique continuation property. That is, the zero on each geodesic of the solution in a real analytic hypersurface for second order anisotropic hyperbolic systems with real analytic coefficients can be continued along this curve.

     

Advanced process device technology for 0.3-μm high-performancebipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm², and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (f_T) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f_T and base resistance is also discussed     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

A spot-size transformer based on mode interference

A novel mode-size transformer based on interference between guided and leaky modes is proposed and analyzed. Simulation shows significant improvement in spot-size transform efficiency per unit length, in comparison with the conventional tapered waveguide mode size converters based on mode evolution. Owing to its structural simplicity, easy fabrication is another merit of the new spot-size transformer     

A novel on-chip electrostatic discharge (ESD) protection withcommon discharge line for high-speed CMOS LSIs

A novel on-chip electrostatic discharge (ESD) protection for high-speed CMOS LSI's that operate at higher than 500 MHz has been developed. Introduction of a newly developed common discharge line (CDL) can completely eliminate the protection device influence on the inner circuit operation. This enables minimization of the I/O capacitance by shrinking the dimension of the output transistor, which also serves as a protection device in conventional devices. This new protection (CDL protection) was applied to a high-speed DRAM of which I/O pin capacitance specification is 2 pF. As a result, the ESD tolerance of 4 kV for the charged device model test, 4 kV for the human body model test, and 700 V for the machine model test were obtained. In addition, the DRAM data rate higher than 660 MHz at room temperature was achieved. The results show significant improvement for both ESD and the I/O capacitance, compared with the conventional structure     

Nondestructive readout mode static induction transistor (SIT) photosensors

The nondestructive readout (NDRO) performance of two static induction transistor (SIT) photosensors, a 40×40 pixel area array and a 140-b linear array, is examined. NDRO operation in the SIT sensors is demonstrated by imaging with the area array and by examining the output waveform of the linear array. The charge lost per NDRO cycle in the linear array was 0.014% near the saturation signal level, and no charge loss could be detected at the ⩽0.5 saturation level. NDRO performance in the area array was degraded compared to the linear array, due to the larger value of the load capacitance connected to the output electrode of the SIT. NDRO operation also enables the cancellation of both the photosite reset noise and the signal nonuniformity by subtracting the first NDRO output from the following NDRO outputs, as well as the advantage of monitoring the signal state during the integration period     

Formation of uniform GaAs multi-atomic steps with 20–30 nm periodicity and related structures on vicinal (111)B planes by MBE

We studied morphology of GaAs surfaces and the transport properties of two-dimensional electron gas (2DEG) on vicinal (111)B planes. Multi-atomic steps (MASs) are found on the vicinal (111)B facet grown by molecular beam epitaxy, which will affect electron transport on the facet. We also studied how the morphology of GaAs epilayers on vicinal (111)B substrates depends on growth conditions, especially on the As₄ flux. The uniformity of MASs on the substrates have been improved and smooth surfaces were obtained when the GaAs was grown with high As₄ flux, providing step periodicity of 20 nm. The channel resistance of the 2DEG perpendicular to the MASs is reduced drastically with this smooth morphology. These findings are valuable not only for fabricating quantum devices on the (111)B facets but also those on the vicinal (111)B substrates.     

Development of 170 GHz/500 kW gyrotron

A development of 170GHz/500kW level gyrotron was carried out as R&D work of ITER. The oscillation mode is TE_31,8. In a short pulse experiment, the maximum power of 750kW was achieved at 85kV/40A. The efficiency was 22%. In the depressed collector operation, 500kW/36%/50ms was obtained. The maximum efficiency of 40% was obtained at P_RF=470kW whereas the power decrease by the electron trapping was observed. Pulse extension was done up to 10s at P_RF=170kW with the depressed collector operation. The power was limited by the temperature increase of the output window.