A 0.18 μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier(LNA) is designed for the impulse radio ultra-wideband(IR-UWB) system.The gain-flatten technique is adopted in this UWB LNA.Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product(GBW).Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations.The prototype is fabricated in the SMIC 0.18μm RF CMOS process.Measurement results show a 3-dB gain band...     

A 3-5 GHz CMOS UWB power amplifier with±8 ps group delay ripple

A differential power amplifier(PA),designed using the linear-phase filter model,for a BPSK modulated ultra-wideband(UWB) system operating in the 3-5 GHz frequency range is presented.The proposed PA was fabricated using 0.18μm SMIC CMOS technology.To achieve sufficient linearity and efficiency,this PA operates in the class-AB region,delivering an output power of 8.5 dBm at an input-1 dB compression point of -0.5 dBm.It consumes 28.8 mW, realizing a flat gain of 9.11±0.39 dB and a very low group delay ripp...     

一种用于3-5GHz IR-UWB的0.18um CMOS BPSK 调制发射机

This paper presents a transmitter IC with BPSK modulation for an ultra-wide band system. It is based on up-conversion with a high linearity passive mixer. Unlike the traditional BPSK modulation scheme, the local oscillator (LO) is modulated by the baseband data instead of the pulse. The chip is designed and fabricated by standard 0.18 μ m CMOS technology. The transmitter achieves a high data rate up to 400 Mbps. The amplitude of the pulse can be adjusted by the amplitude of the LO and the bias current of the driver amplifier. The maximum peak-to-peak amplitude of the pulse is 600 mV. It consumes only 20.3 mA current with a supply voltage of 1.8 V when transmitting a pulse at the maximum data rate. The energy efficiency is 91.4 pJ/pulse. The die area is 1.4 × 1.4 mm².     

一种用于电视协调器的CMOS无电感互补噪声抵消低噪声放大器设计

本文介绍了一个用于电视协调器的CMOS无电感互补噪声抵消低噪声放大器。放大器包括一个共栅极和一个共源级,实现单端转差分的功能。采用的互补结构能够节省功耗和改善噪声系数。线性度也通过采用多个晶体管并联技术来增强。芯片采用SMIC 0.18μm CMOS 工艺。测试结果表明,在50MHz到860MHz频段内,电压增益达到13.5到16dB,噪声系数小于4.5dB,最小达到2.9dB,在860MHz频率处,输入1dB压缩点为-7.5dBm。核心电路在1.8V电源电压下,消耗6mA电流,芯片面积是0.2×0.2mm2     

A 0.18μm CMOS inductorless complementary-noise-canceling-LNA for TV tuner applications

This paper presents an inductorless complementary-noise-canceling LNA(CNCLNA) for TV tuners.The CNCLNA exploits single-to-differential topology,which consists of a common gate stage and a common source stage. The complementary topology can save power and improve the noise figure.Linearity is also enhanced by employing a multiple gated transistors technique.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed CNCLNA achieves 13.5-16 dB voltage gain from 50 to 860 MHz,...     

A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

正This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz.The Gilbert mixer is known for its perfect port isolation and bad noise performance.The noise cancellation technique of LNA can be applied here to have a better NF.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz,an average noise figure of 5 dB and a minimum value of 4.3 dB.The core area is 0.6 x 0.45 mm~2.     

基于优化时间重叠技术的并行流水线A/D转换器

提出了一种基于优化时间重叠技术的10位300 MHz采样率4路并行流水线A/D转换器的设计方法,该方法降低了对运算放大器的要求。通过理论计算和实例设计,证明了此低功耗设计方法的显著效果。设计了一个用于前端的运算放大器,在CSM 0.35μm CMOS工艺、3.3 V电源电压下,该运放的增益为106 dB,单位增益带宽为402 MHz,建立时间为8.8 ns。采用优化时间重叠技术后,可满足4路并行300 MHz采样率的要求,功耗仅为8.57 mW,可大大降低整个并行流水线A/D转换器的功耗。     

机载窄带多路视频传输系统设计

为了满足两路视频的实时窄带无线传输要求,设计并实现了一种JlEG2000视频压缩解压缩与多路数据传输系统.系统总线带宽为3.84Mbit/s,视频信号采集、压缩、下传、回放的延时控制在300ms以内.本系统由APV202来完成视频压缩与解压缩,由FPGA来实现两路视频数据和一路遥感数据的封装及传输.用ATmega128...     

一个用于非相干脉冲超宽带的能量检测接收机

本文提出一个用脉冲超宽带体制的非相干接收机 。提出的接收机前端包含高增益地噪声放大器,一个高频检波器以及用于放大检波后信号的中频放大器。低噪声放大器采用了电容交叉耦合和电流复用技术用于在适当功耗下获得高增益和低噪声性能。检波器部分包含平方器和积分器。在400MHz的脉冲速率下,整个电路在1.8V电源下消耗电流41.2mA。最终的能量利用率为0.19nJ每脉冲。芯片在0.18 um CMOS工艺下实现,芯片面积为2.11.4 mm2 ,核心面积为1.70.98 mm2.     

采用噪声抵消技术的无电感宽带低噪声放大器

设计了一款多用途、宽带、无电感的低噪声放大器。放大器的第1级为单端输入差分输出结构,采用了噪声抵消技术来降低噪声;第2级引入有源感性负载,并通过电阻负反馈来扩展带宽。采用TSMC 130 nm工艺对电路进行仿真,后仿结果表明,在0.4~6.2 GHz带宽范围内,S21为19 dB,噪声系数为1.9~2.5 dB,功耗为9.6 mW,电路核心面积为0.08 mm²。