Horizontal InAs nanowire transistors grown on patterned silicon-on-insulator substrate

High-density horizontal InAs nanowire transistors are fabricated on the interdigital silicon-on-insulator substrate. Hexagonal InAs nanowires are uniformly grown between face-to-face (111) vertical sidewalls of neighboring Si fingers by metal-organic chemical vapor deposition. The density of InAs nanowires is high up to 32 per group of silicon fingers, namely an average of 4 nanowires per micrometer. The electrical characteristics with a higher on/off current ratio of 2×10⁵ are obtained at room temperature. The silicon-based horizontal InAs nanowire transistors are very promising for future high-performance circuits.     

利用键合方法转移薄膜材料

阐述了利用键合方法转移薄膜材料的技术及其应用。最人竞争力的转移固体薄膜技术主要有键合加选择性腐蚀工艺和注氢智能剥离工艺，这种技术解决了外延生长难以解决的晶格失配问题，为改善器件结构及性能提供了巨大的潜力。     

Quantum transport characteristics in single and multiple N-channel junctionless nanowire transistors at low temperatures

Single and multiple n-channel junctionless nanowire transistors(JNTs) are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures(10 K–100 K) and variable drain bias voltages(10 mV–90 mV). Transfer characteristics exhibit current oscillation peaks below flat-band voltage(VFB) at temperatures up to 75 K,which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional(1D) channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.     

硅片键合过程中的接触面积

给出了估计硅片在键合过程中实际接触面积的理论模型.模型描述了硅片表面的凸起分布及其弹性形变对接触面积的影响.对于满足键合条件的硅片表面,荷载压力和表面吸附是促使接触面积增加的主要因素.     

硅纳米结构晶体管中与杂质量子点相关的量子输运

在小于10 nm的沟道空间中,杂质数目和杂质波动范围变得十分有限,这对器件性能有很大的影响.局域纳米空间中的电离杂质还能够展现出量子点特性,为电荷输运提供两个分立的杂质能级.利用杂质原子作为量子输运构件的硅纳米结构晶体管有望成为未来量子计算电路的基本组成器件.本文结合安德森定域化理论和Hubbard带模型对单个、分立和耦合杂质原子系统中的量子输运特性进行了综述,系统介绍了提升杂质原子晶体管工作温度的方法.     

运用两步曝光法减小纳米间隔纳米柱制备中的邻近效应

A two-step exposure method to effectively reduce the proximity effect in fabricating nanometer-spaced nanopillars is presented. In this method, nanopillar patterns on poly-methylmethacrylate （PMMA） were partly crosslinked in the first-step exposure. After development, PMMA between nanopillar patterns was removed, and hence the proximity effect would not take place there in the subsequent exposure. In the second-step exposure, PMMA masks were completely cross-linked to achieve good resistance in inductively coupled plasma etching. Accurate pattern transfer of rows of nanopillars with spacing down to 40 nm was realized on a silicon-on-insulator substrate.     

增强型AlGaN/GaN HEMT器件工艺的研究进展

随着高压开关和高速射频电路的发展,增强型GaN基高电子迁移率晶体管(HEMT)成为该领域内的研究热点。增强型GaN基HEMT只有在加正栅压才有工作电流,可以大大拓展该器件在低功耗数字电路中的应用。近年来,国内外对增强型GaN基HEMT阈值电压的研究主要集中以下两个方面:在材料生长方面,通过生长薄势垒、降低Al组分、生长无极化电荷的AlGaN/GaN异质材料、生长InGaN或p-GaN盖帽层,来控制二维电子气浓度;在器件工艺方面,采用高功函数金属、MIS结构、刻蚀凹栅、F基等离子体处理,来控制表面电势,影响二维电子气浓度。从影响器件阈值电压的相关因素出发,探讨了实现和优化增强型GaN基HEMT的各种工艺方法和发展方向。     

AlGaN/GaN HEMT器件工艺的研究进展

首先论述了Al GaN/GaN高电子迁移率晶体管(HEMT)在微波大功率领域的应用优势和潜力;其次,介绍并分析了影响Al GaN/GaN HEMT性能的主要参数,分析表明要提高Al-GaN/GaN HEMT的频率和功率性能,需改善寄生电阻、电容、栅长和击穿电压等参数。然后,着重从材料结构和器件工艺的角度阐述了近年来Al GaN/GaN HEMT的研究进展,详细归纳了目前主要的材料生长和器件制作工艺,可以看出基本的工艺思路是尽量提高材料二维电子气的浓度和材料对二维电子气的限制能力的同时减小器件的寄生电容和电阻,增强栅极对沟道的控制能力。另外,根据具体情况调节栅长及沟道电场。最后,简要探讨了Al GaN/GaN HEMT还存在的问题以及面临的挑战。     

硅片接触表面的弹性形变范围

提出了键合过程中硅片接触的一种弹性形变模型。接触硅片表面的周期性应力场决定着接触表面形貌的变化。Airy应力函数给出了满足键合界面应力平衡微分方程的解。根据应变场的分布,给出了硅片键合界面弹性形变的范围。