催化剂对煤着火特性的影响 Ⅱ.不同催化剂对煤催化着火的影响

通过测定煤的着火点研究了不同催化剂对大同烟煤和晋城无烟煤的催化着火的影响。结果表明,催化剂化学组成是决定催化作用大小的一个重要的因素,具有同一碱金属离子,不同阴离子的催化剂酸性越强,催化作用越弱,其催化活性顺序为OH~->CO_3~(2-)>Cl~->SO_4~(2-);具有同一阴离子,不同碱金属或碱土金属阳离子的催化作用可用“电子转移学说”来解释,其催化作用的大小,随相应的碱金属,碱土金属的第一电离能的减少而增加。     

Investigation of the characteristics of GIDL current in 90nm CMOS technology

A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias $V_{\rm D}$ has a strong effect on GIDL current as compared with the gate bias $V_{\rm G}$ at the same drain--gate voltage $V_{\rm DG}$. It is found that the difference between $I_{\rm D}$ in the off-state $I_{\rm D}-V_{\rm G}$ characteristics and the corresponding one in the off-state $I_{\rm D}-V_{\rm D}$ characteristics, which is defined as $I_{\rm DIFF}$, versus $V_{\rm DG}$ shows a peak. The difference between the influences of $V_{\rm D}$ and $V_{\rm G}$ on GIDL current is shown quantitatively by $I_{\rm DIFF}$, especially in 90nm scale. The difference is due to different hole tunnellings. Furthermore, the maximum $I_{\rm DIFF }$($I_{\rm DIFF,MAX})$ varies linearly with $V_{\rm DG}$ in logarithmic coordinates and also $V_{\rm DG}$ at $I_{\rm DIFF,MAX}$ with $V_{\rm F}$ which is the characteristic voltage of $I_{\rm DIFF}$. The relations are studied and some related expressions are given.     

Comparison of hot-hole injections in ultrashort channel LDD nMOSFETs with ultrathin oxide under an alternating stress

The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain (LDD) nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injections, i.e. low gate voltage hot hole injection (LGVHHI), gate-induced drain leakage induced hot-hole injection (GIDLIHHI) and substrate hot-hole injection (SHHI), have different influences on the devices damaged already by the previous hot electron injection (HEI) because of the different locations of trapping holes and interface states induced by the three types of injections, i.e. three types of stresses. Experimental results show that GIDLIHHI and LGVHHI cannot recover the degradation of electron trapping, but SHHI can. Although SHHI can recover the device's performance, the recovery is slight and reaches saturation quickly, which is suggested here to be attributed to the fact that trapped holes are too few and the equilibrium is reached between the trapping and releasing of holes which can be set up quickly in the ultrathin oxide.     

CAD／CAPP／CAM集成技术的初步分析

针对目前商用软件在CAD／CAPP／CAM(简称3C)集成开发上存在的问题，对3C集成的方式和关键技术进行了初步的分析。     

反向衬底偏压下纳米N沟道金属氧化物半导体场效应晶体管中栅调制界面产生电流特性研究

研究了反向衬底偏压V_B下纳米N沟道金属氧化物半导体场效应晶体管中栅调制界面产生(GMG)电流I_GMG特性, 发现I_GMG曲线的上升沿与下降沿随着|V_B|的增大向右漂移. 基于实验和理论模型分析, 得出了V_B与这种漂移之间的物理作用机制, 漂移现象的产生归因于衬底偏压V_B 调节了表面电势φ_s在栅电压V_G 中的占有比重: |V_B|增大时相同V_G下φ_s会变小, φ_s 的变化继而引发上升沿产生率因子g_r减小以及下降沿产生率因子g_f增大. 进一步发现I_GMG 上升沿与下降沿的最大跨导G_MR, G_MF 在对数坐标系下与V_B成线性关系, 并且随着|V_B|增加而增大. 由于漏电压V_D在I_GMG 上升沿与下降沿中的作用不同, 三种V_D下G_MR-V_B曲线重合而G_MF-V_B曲线则产生差异. 增大V_D 会增强g_f 随V_G的变化, 因此使得给定V_B 下的G_MF变大. 同时这却导致了更大V_D下G_MF-V_B 曲线变化的趋势减缓, 随着V_D从0.2 V变为0.6 V, 曲线的斜率s从0.09减小到0.03. 关键词： 产生电流 表面势 衬底偏压 N沟道金属氧化物半导体场效应晶体管     

超薄栅超短沟LDD nMOSFET中栅电压对栅致漏极泄漏电流影响研究

本文研究了90nm CMOS工艺下栅氧化层厚度为1.4 nm沟道长度为100 nm的轻掺杂漏(LDD)nMOSFET栅电压V_G对栅致漏极泄漏 (GIDL)电流I_d的影响,发现不同V_G下ln (I_d/(V_DG-1.2))-1/(V_DG-1.2)曲线相比大尺寸厚栅器件时发生了分裂现象. 通过比较V_G变化下ln(I_d/(V_DG-1.2))的差值,得出V_G与这种分裂现象之间的作用机理,分裂现象的产生归因于V_G的改变影响了GIDL电流横向空穴隧穿部分所致. 随着|V_G|的变小,ln(I_d/(V_DG-1.2))曲线的斜率的绝对值变小.进一步发现不同V_G对应的ln (I_d/(V_DG-1.2))曲线的斜率c及截距d与V_G呈线性关系,c,d曲线的斜率分别为3.09和-0.77. c与d定量的体现了超薄栅超短沟器件中V_G对GIDL电流的影响,基于此,提出了一个引入V_G 影响的新GIDL电流关系式.     

基于Comsol的双环磁控溅射靶的磁场模拟分析

影响靶材刻蚀特性的主要因素来自平行靶面的磁场分布,为了得到更优的磁控靶结构参数以实现靶面水平磁感应强度的均匀分布,本文利用Comsol软件对双环磁控溅射靶的靶面水平磁感应强度分布进行模拟分析,得出了当内磁环高度h=10 mm,外磁环与靶材间距d=7 mm时的靶面水平磁感应强度分布较为理想.除此之外,还探讨了加装导磁片对靶面水平磁感应强度的影响,结果表明采用适当的导磁片长度、厚度以及导磁片与磁环之间的间距,对靶材的水平磁场强度分布具有调节作用.在工程应用中,技术人员可以事先对靶材结构进行模拟优化以节省生产周期和成本,对实际生产具有指导意义.     

W-Plug通孔电迁移研究

We analyze the failure mechanism of W-plug via electromigration made in a 0.5-μm CMOS SPTM process. Failure occurs at the top or bottom of a W-plug via. We design a series of via chains, whose size ranges from 0.35 to 0.55μm. The structure for the via electromigration test is a long via chain, and the layer in the via is Ti/TiN/W/TiN. Using a self-heated resistor to raise the temperature of the via chain allows the structure to be stressed at lower current densities, which does not cause significant joule heating in the plugs. This reduces the interaction between the plug and the plug contact resistance and the time-to-failure for the via chain. The lifetime of a W-plug via electromigration is on the order of 3×10^7S, i.e., far below the lifetime of metal electromigration. The study on W-plug via electromigraion in this paper is beneficial for wafer level reliability monitoring of the ultra-deep submicron CMOS multilayer metal interconnect process.     

一种三维刚体运动参数鲁棒估计的神经算法

该文提出一种基于特征点匹配的刚体运动参数估计方法。在运动估计线性算法的基础上,文中利用全最小二乘(TLS)方法来进行求解,并建立次分量提取神经元来获得该全最小二乘解。基于测量数据中出格点(Outlier)的存在,我们在神经元的权值学习规则中引入鲁棒估计思想。实验结果表明,该方法能有效地克服出格点产生的误差,准确地估计出刚体的三维运动参数,比较令人满意。     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).