Effect of substrate bias on negative bias temperature instability of ultra-deep sub-micro p-channel metal--oxide--semiconductor field-effect transistors

The effect of substrate bias on the degradation during applying a negative bias temperature (NBT) stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability (NBTI) is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electron--hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.     

Characteristics and parameter extraction for NiGe/n-type Ge Schottky diode with variable annealing temperatures

Current transport mechanism in Ni-germanide/n-type Ge Schottky diodes is investigated using current--voltage characterisation technique with annealing temperatures from 300~\duto 500~\du. Based on the current transport model, a simple method to extract parameters of the NiGe/Ge diode is presented by using the $I$--$V$ characteristics. Parameters of NiGe/n-type Ge Schottky diodes fabricated for testing in this paper are as follows: the ideality factor $n$, the series resistance $R_{\rm s}$, the zero-field barrier height $\phi _{\rm b0}$, the interface state density $D_{\rm it}$, and the interfacial layer capacitance $C_{\rm i}$. It is found that the ideality factor $n$ of the diode increases with the increase of annealing temperature. As the temperature increases, the interface defects from the sputtering damage and the penetration of metallic states into the Ge energy gap are passivated, thus improving the junction quality. However, the undesirable crystallisations of Ni-germanide are observed together with NiGe at a temperature higher than 400~\du. Depositing a very thin ($\sim $1~nm) heavily Ge-doped $n^{+}$ Ge intermediate layer can improve the NiGe film morphology significantly.     

功率合成电路在氮化镓放大器中的应用

针对氮化镓大功率放大器,由于传统1/4λ枝节线的电桥互耦造成放大器的直流自激和低频自激,在传统1/4λ传输枝节的Wilkinson电桥的基础上,结合氮化镓器件尺寸,设计出以3/4λ传输枝节的Wilkinson电桥为功率分配器/合成器。其输出端口尺寸为27.2mm。在8GHz～9GHz内,插入损耗<1dB,输出端口隔离度>14dB,端口回波损耗>9dB。利用实验室自制的SiC材料衬底的2.5mm栅宽GaN HEMT器件为放大单元,设计完成了两路合成放大器,在8GHz连续波条件下,放大器饱和输出功率为41.46dBm,合成效率为82.3%。通过分析发现,放大器合成效率的下降主要是由每路放大单元特性不一致和功率合成网络损耗所造成的。