80dB动态范围，用于低中频结构GSM接收机的ΣΔ调制器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度ΣΔ调制器.该调制器采用3阶单环单比特的结构,电路使用全差分开关电容结构实现,并在0.6μm 2P2M CMOS工艺下流片验证.调制器使用全差分±1V参考电压,工作在26MHz采样频率,过采样率为64.测试结果表明,在200kHz信号带宽内,调制器达到80.6dB动态范围,峰值SNDR达到71.8dB,峰值SNR达到73.9dB.整个调制器电源电压为5V,静态功耗为15mW.     

A robust and simple two-mode digital calibration technique for pipelined ADC

This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters (ADC).The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom(PN) sequence injection capacitors at the ADC initialization,while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation.The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain,but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors.The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology.The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process.Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage,the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB,respectively.With the calibration,the maximum integral nonlinearity (INL) of the ADC reduces from 4.75-LSB to 0.65-LSB,while the ADC core consumes 82-mW at 3.3-V power supply.