电话防盗打器

电话防盗打器陈肇基目前电话被盗打现象仍然存在，这里介绍两种各具特色的防盗打器，仅供读者参考。这两种防盗打器主要优点是，不需要外接电源，它们的工作电源由电话线供给；另外防盗打器体积很小，可以安装在电话机内，只要安装、焊接无误，简便的调试，便可使用。电路...     

先进的移动卫星通信综合系统

先进的移动卫星通信综合系统陈肇基自从模拟式蜂窝状移动电话问世以来，全世界移动电话用户的发展，每年增长超过４０％。目前西欧和美国的用户已超过１千万户，并从模拟制逐步过渡到数字蜂窝状移动电话制式，简称ＧＳＭ。ＧＳＭ虽称为全球性的移动电话，但蜂窝状移动电话...     

DMOS辐照正空间电荷阈值电压模型

提出了一种DMOS辐照正空间电荷闽值电压模型。基于沟道杂质的非均匀分布，借助镜像法，导出辐照正空间电荷与沟道电离杂质的二维场和二维互作用势；求解泊松方程，由此给出DMOS辐照正空间电荷阈值电压模型表示式。该模型的解析解与MEDICI仿真的数值解吻合。     

带p埋层表面注入硅基LDMOS模型与优化

提出一种带p埋层的表面注入硅基LDMOS高压器件新结构,称为BSI LDMOS(surface implanted LDMOS with p buried layer).通过表面注入n 薄层降低导通电阻,p埋层不但改善横向表面电场分布,提高击穿电压,而且增大漂移区优化浓度.求解电势的二维Poisson方程,获得表面电场和击穿电压的解析式,研究结构参数对表面电场和击穿电压的影响,数值与解析结果吻合较好.结果表明:与常规结构相比较,BSI LDMOS大大改善了击穿电压和导通电阻的折衷关系.     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n⁺-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the E_I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.     

Monolithic integration of AlGaN/GaN metal—insulator field-effect transistor with ultra-low voltage-drop diode for self-protection

In this paper, we present a monolithic integration of self-protected AlGaN/GaN metal-insulator field-effect transistor (MISFET). An integrated field-controlled diode on the drain side of the AlGaN/GaN MISFET features self-protected function at reverse bias. This diode takes advantage of the recessed-barrier enhancement-mode technique to realize an ultra-low voltage drop and a low turn-ON voltage. In the smart monolithic integration, this integrated diode can block reverse bias (>70 V/μm) and suppress the leakage current (<5×10^-11 A/mm). Compared with conventional monolithic integration, the numerical results show that the MISFET integrated with a field-controlled diode leads to a good performance for smart power integration. And the power loss is lower than 50% in conduction without forward current degeneration.     

A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon on insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.     

Novel high-voltage power device based on self-adaptive interface charge

This paper presents a novel high-voltage lateral double diffused metal--oxide semiconductor (LDMOS) with self-adaptive interface charge (SAC) layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer (E_I) and increase breakdown voltage (BV). The BV and E_I of SAC LDMOS increase to 612 V and 600 V/μm from 204 V and 90.7 V/μm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of η which present the enhanced ability of interface charge on E_I are defined and analysed.     

埋空隙PSOI结构的耐压分析

提出了一种埋空隙PSOI (APSOI) RESURF器件结构,此结构利用空隙相对低的介电系数,在器件纵向突破了传统SiO2埋层的耐压关系,提高了击穿电压;硅窗口的存在缓解了有源区的自热效应;不同衬底的场调制作用进一步优化了表面电场分布. 在相同击穿电压条件下,此结构较一般PSOI结构只需1/4厚度的埋层,当漂移区厚度和埋层厚度均为2μm时可获得600V以上的击穿电压.