450nm GaN基半导体激光器腔面反射率的优化

分析腔面反射率对GaN基半导体激光器斜率效率和输出功率的影响,并对出射波长为450 nm的激光器进行实验验证。结果表明,对于非对称谐振腔结构,通过优化腔面反射率,可以抑制空间烧孔非线性效应,提高器件的微分量子效率和最大输出功率。当前腔面反射率为5%时,斜率效率大于1.3 W·A~(-1),并在3 A的连续工作电流下,获得了2.6 W的高功率输出。     

具有L型低阻导电通道的介质场增强SOI LDMOS

A low specific on-resistance（R on;sp/ SOI NBL TLDMOS（silicon-on-insulator trench LDMOS with an N buried layer） is proposed. It has three features： a thin N buried layer（NBL） on the interface of the SOI layer/buried oxide（BOX） layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the R on;sp. Second, in the y-direction, the BOX＇s electric field（E-field） strength is increased to 154 V/ m from48 V/ m of the SOI Trench Gate LDMOS（SOI TG LDMOS） owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage（BV）, but also reduces the cell pitch and R on;sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 m, and decreases the R on;sp by 80% at the same BV.     

提高超大光腔波导结构半导体激光器功率效率的设计考虑

对976 nm波段超大光学腔结构半导体激光器的外延和谐振腔设计进行了数值研究。在量子阱层的下方和上方设计了模式控制层,以抑制快轴高阶模的激射。通过能带结构的调控抑制了电子泄漏,调控使得电子势垒从p波导层到p包层增加。优化后的外延结构内部损耗为0.66 cm^-1,内部量子效率为0.954,远场发散角半高全宽为17.4°。对于谐振腔设计,提出了沿谐振腔线性电流分布结构,以减少空间烧孔效应,这使激光器在20 A时功率提高了1.0 W。采用超大光学腔外延结构的4 mm腔长、100 μm发光区宽度的单管芯片,在25°C连续电流注入下,21 W输出功率时达到约71%的高功率效率。     

高k介质电导增强SOI LDMOS机理与优化设计

本文提出一种高k介质电导增强SOI LDMOS新结构（HK CE SOI LDMOS）,并研究其机理. HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻. 借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系. 结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%–18%,同时比导通电阻降低13%–20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题. 关键词： k介质')" href="#">高k介质 绝缘体上硅 (SOI) 击穿电压 比导通电阻     

色谱用键合固定相的新制备方法——冷等离子体法

〕用冷等离子体技术建立了色谱键合固定相的新制备方法。考察了不同的处理条件,得到了满意的结果。用新方法制得的键合固定相的色谱分离能力（对六种一元醇的混合物而言）与常规方法制得的键合固定相相当。新方法与传统方法比较,具有节约时间和化学试剂的优点。     

光谱法研究哈巴俄苷与人血清白蛋白的结合反应

在不同温度及模拟血液pH值条件下,采用荧光光谱法和紫外-可见吸收光谱法研究了哈巴俄苷(Harpagoside, HAR)与人血清白蛋白(Human serum albumin, HSA)的结合反应.结果表明,HAR有规律地使HSA内源荧光猝灭,猝灭常数随温度升高而降低,其猝灭机制为两者形成复合物而引起的的静态猝灭;不同条件下两者结合常数KA均大于105 L/mol,结合位点数n≈1.由Van′t Hoff方程计算获得了不同条件下HAR与HSA相互作用的热力学参数,由ΔG、ΔH和ΔS均小于0可知,两者结合的主要作用力是氢键和范德华力,且两者结合是吉布斯自由能降低的自发过程.根据F(o)rster非辐射转移理论计,计算了不同条件下HAR与HSA的结合距离r在4.01~4.28 nm范围内,表明两者结合过程发生了非辐射能量转移.同步荧光光谱表征结果表明,HAR使HSA的色氨酸和酪氨酸残基所处的微环境极性增强,疏水性减弱,导致HSA构象发生了一定程度的改变.     

High voltage SOI LDMOS with a compound buried layer

An SOI LDMOS with a compound buried layer (CBL) was proposed. The CBL consists of an upper buried oxide layer (UBOX) with a Si window and two oxide steps, a polysilicon layer and a lower buried oxide layer (LBOX). In the blocking state, the electric field strengths in the UBOX and LBOX are increased from 88 V/μm of the buried oxide (BOX) in a conventional SOI (C-SOI) LDMOS to 163 V/μm and 460 V/μm by the holes located on the top interfaces of the UBOX and LBOX, respectively. Compared with the C-SOI LDMOS, the CBL LDMOS increases the breakdown voltage from 477 to 847 V, and lowers the maximal temperature by 6 K.     

大功率780nm半导体激光器的设计与制备

设计并制备了一款780 nm半导体激光器,并进行了外腔反馈锁模研究。利用金属有机化学气相沉积技术制备了激光器外延层,采用GaAsP/GaInP作为量子阱/波导层有源区,限制层采用低折射率AlGaInP材料。采用超高真空解理钝化技术,在激光器腔面蒸镀无定形ZnSe钝化层。未钝化器件在输出功率2.5 W时发生腔面灾变损伤（COD）,钝化后器件未发生COD现象,电流在10 A时输出功率10.1 W,电光转换效率54%。体布拉格光栅（VBG）外腔锁定前后,器件的光谱半峰全宽分别为2.6 nm和0.06 nm,VBG变温调控波长范围约230 pm。     

色谱用键合固定相新制备方法的研究——冷等离子体技术的应用(初报)

键合固定相的制备一般通过硅烷化或酯化反应来进行。反应条件虽易控制,但反应后硅胶类载体表面往往或多或少残留一些未反应的羟基,使固定相具有双官能性能。制备过程一般也比较繁复,而且许多固定液很难用常规化学方法键合上去。鉴于冷等离子体出色的引发反应和表面处理能力,我们提出了用冷等离子体技术研制键合固定相的设想。     

A low specific on-resistance SOI MOSFET with dual gates and recessed drain

A low specific on-resistance (R_on,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R_on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R_on,sp of 4.151 mΩ·cm² (V_GS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R_on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.