32.
Metal-oxide-semiconductor (MOS) storage capacitors based on electron beam deposited Y
2O
3 extrinsic dielectric on Si show changes in capacitance density depending on the amorphous and crystalline phases. Bias stress
cycle-dependent changes in capacitance density occur due to the non-equilibrium nature of defect states at the Y
2O
3/Si interface after O
2 annealing as a result of the emergence of a 4–8 nm thick SiO
2 film at the interface. Leakage currents show instability under repeated dc bias stress, the nature and extent of which depend
upon the structure of the Y
2O
3 gate dielectric and the polarity of dc bias. With amorphous Y
2O
3, leakage currents drift to lower values under gate injection due to electron trapping, and to higher values under Si-injection
due to the generation of holes. Though leakage current drift is minimal for crystalline Y
2O
3, its magnitude increases as the energy of injected electrons from mid-gap states is low and the local field due to asperity
is high. The emergence of interfacial SiO
2 reduces the magnitude of Si-injection leakage current substantially, but causes transient changes resulting in switching
to higher values at a threshold dc bias. Thermal detrapping of holes and reverse bias stress studies confirm that the instability
of current is caused by an increase in the cathodic field from hole trapping at interface states. Leakage current instability
limits the application of extrinsic high dielectric constant dielectrics in a high density DRAM storage capacitor, unless
a new interface layer scheme other than SiO
2 and a method to form a defect-free dielectric layer can be implemented.
Received: 29 October 2001 / Accepted: 22 April 2002 / Published online: 4 December 2002
RID="*"
ID="*"Corresponding author. Fax: +1-413/545-4611, E-mail: rastogi@ecs.umass.edu
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