宽谱高分辨平场凹面全息光栅光谱仪设计

为了获得宽谱、高分辨的平场凹面全息光栅,将全息凹面光栅理论、遗传算法、衍射级次空间共用和同时消像差思想融合在一起,提出设计宽谱、高分辨平场凹面全息光栅的方法,给出了实际设计步骤。通过Zemax软件光线追迹仿真具体实例,给出了200～800nm波段的点列图变化曲线[均方根(RMS)约为11μm],以10μm×1mm狭缝入射,其光照度光谱图显示光谱分辨率在200～400nm波段为0.25nm,在400～800nm波段为0.5nm。该方法可以用于设计小型化、实用化的宽谱和高分辨平场凹面全息光栅光谱仪光学系统。     

A fast improved fat tree encoder for wave union TDC in an FPGA

Up to now, the wave union method can achieve the best timing performance in FPGA-based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands that the encoder convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder (IFTE) to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constraints were required; therefore, this IFTE structure could also be further applied in other delay-chain-based FPGA TDCs.     

A new method of waveform digitization based on time-interleaved A/D conversion

Time interleaved analog-to-digital conversion (TIADC) based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limitation in hardware design and to implement the mismatch correction algorithm in real time,this paper proposes a fully parallel correction algorithm. A 12-bit 1-Gsps waveform digitizer with ENOB around 10.5 bit from 5 MHz to 200 MHz is implemented based on the real-time correction algorithm.     

Proposal of the readout electronics for the WCDA in the LHAASO experiment

The LHAASO(Large High Altitude Air Shower Observatory)experiment is proposed for a very high energy gamma ray source survey,in which the WCDA(Water Cherenkov Detector Array)is one of the major components.In the WCDA,a total of 3600 PMTs are placed under water in four ponds,each with a size of150 m×l50 m.Precise time and charge measurement is required for the PMT signals,over a large signal amplitude range from a single P.E.(photo electron)to 4000 P.E.To fulfill the high requirement of a signal measurement in so many front end nodes scattered in a large area,special techniques are developed,such as multiple gain readout,hybrid transmission of clocks,commands and data,precise clock phase alignment and new trigger electronics.We present the readout electronics architecture for the WCDA and several prototype modules,which are now being tested in the laboratory.     

激光诱导击穿光谱对不规则未知镀层样品的分析

传统经典的镀层分析方法分析速度慢,对于不规则镀层样品较难分析,文中在最佳分析条件下,采用激光诱导击穿光谱法对两块不规则未知镀层样品进行分析,镀层分析曲线表明,两块未知镀层样品采用渗锌工艺制备而成,镀层表面的锌、 铁元素是主量元素,少量的铬起钝化作用,镀层界面下则是中低合金钢,用一套中低合金钢标准样品建立校准曲线,准确分析了镀层界面下中低合金钢的化学成分及Cr和Mo元素在镀层表面的含量变化情况,从而对未知不规则镀层样品的化学成分有一个深入的了解。     

基于开关电容阵列ASIC芯片的多通道波形数字化系统设计

基于开关电容阵列（SCA）技术可以实现超高速的波形数字化。本研究是基于实验室设计完成的FEL_SCA芯片进行8通道2 Gsps的波形数字化模块的设计,电路的配置和读出控制功能集成在单个FPGA中完成,此外该模块还包含SDRAM缓存及USB接口。目前已在实验室环境下对其进行了直流电压测试、瞬态波形测试和带宽测试,测试结果表明,在FEL_SCA芯片的输入动态范围100 mV~1 V之间,本波形数字化模块的INL好于1%,通道的RMS噪声约为1.76 mV,带宽约为450 MHz,达到设计目标。Switched Capacitor Arrays (SCAs) can be employed to achieve high speed waveform digitization. In this paper, we designed an 8-channel 2 Gsps waveform digitization module using four SCA chips named FEL_SCA which was designed in our laboratory. In this module, we used a FPGA device for data readout and circuit configuration. Besides, a 128 Mb SDRAM and USB interface were integrated in this module. We have also conducted DC voltage tests, transient tests and bandwidth tests on this module. The results indicate that in the signal voltage range 100 mV~1 V, the INL is better than 1%, the RMS noise is about 1.76 mV and the -3 dB input bandwidth is 450 MHz.     

12 bit 30 MSPS逐次比较型ADC的测试

针对物理实验读出的需求设计了一款低功耗12 bit 30 MSPS逐次比较型模数变换器（Analog-to-Digital Converter,ADC）芯片,为评估其性能指标参数,需进行系统的测试。在本研究工作中构建了测试系统,然后按照IEEE标准进行了系统的测试和分析。测试结果表明,输入信号在基带范围内ADC有效位（Effective Number Of Bit,ENOB）约为9 bit,达到了本版本芯片的设计指标。同时,综合分析静态性能与动态性能测试结果,可以通过优化逐次比较型ADC中电容阵列电容失配参数,进一步提升ADC的非线性指标,为下一版芯片的改进设计提供了参考依据。Aiming at the requirement of readout electronics in physics experiments, a 12 bit 30 MSPS successiveapproximation-register (SAR) analog-to-digital converter (ADC) with low power consumption has been designed. To evaluate the performance of this ASIC, we conducted a series of tests. We set up a test system, and we tested the ADC according to IEEE std 1241-2010. The test results indicate that the effective number of bit (ENOB) of the ADC is around 9 bits when the input signal is in the first Nyquist zone, which has met the design requirements. According to the results of dynamic and static tests of this ADC, we found that the non-linearity performance of this ASIC can be further enhanced by improving the mismatching among the capacitor array, and this provides important information for the design of the second version of this ADC.     

大跨度叠合梁斜拉桥多维多点非平稳随机地震响应分析

为研究地震动非平稳特性对大跨度叠合梁斜拉桥随机地震响应的影响,采用绝对位移求解的虚拟激励法在通用有限元软件中对某座叠合梁斜拉桥进行多维多点非平稳随机地震响应分析.研究结果表明:采用绝对位移求解的虚拟激励法,能在通用有限元软件中高效地实现对大跨度叠合梁斜拉桥多维多点非平稳随机地震响应分析;设计中假定地震动平稳性,得到的结果偏于保守;行波效应对大跨度叠合梁斜拉桥结构响应有显著影响,考虑行波效应对主塔塔顶位移和塔底内力是有利的,但应注意其对主梁跨中位移和内力的不利影响.     

新型含氟聚苯撑乙烯的合成及电致发光性能

设计并合成了两个不同烷氧基增溶的结构新颖的含氟聚苯撑乙烯Pa, Pb和共聚物Pc. 通过核磁共振和元素分析对其结构进行了表征, 通过热重分析、凝胶色谱测定了其热分解温度和分子量及分布; 紫外-可见吸收光谱仪和荧光分光光度计测得其吸收-发射光谱. 测量发现热失重曲线拐点温度超过400 ℃. 由2-乙基己基增溶的Pa和Pc具有优异的溶解性, 固态荧光发射波长分别为499和585 nm, 相应比PPV和MEH-PPV稍有蓝移. 应用旋转涂膜的方法制作Pa和Pc的双层器件(ITO/PEDOT/Polymer/Ba/Al), 电致发光波长分别为494和604 nm, 器件均具有较低的启动电压(4 V左右), 分别在24和15 V时达到最大亮度598和203 cd•m^－2, 而此时电流密度分别为100和80 mA•cm^－2.     

光纤法布里-珀罗传感器光纤端面反射率优化

讨论了反射光纤端面反射率对（F-P）传感器输出信号质量的影响,指出反射光纤端面反射率的提高可以克服光在F-P腔内损耗的影响,且对应传感器腔长有和其匹配的最优反射率.为了使传感器在其工作腔长范围内的输出信号整体上具有尽可能好的信号质量,采用最小均方误差法确定了反射光纤端面的最优反射率.仿真证明了采用最优反射率时的信号质量优于采用非最优反射率时的信号质量.