聚氧乙烯功能基复合修饰聚氨酯的合成 及其血液相容性研究(Ⅰ)

通过十八烷基聚氧乙烯和环氧氯丙烷的封端反应制备了α-环氧基-ω-十八烷基聚氧乙烯大单体.并采用BF     

三维超音进气道内外流场的数值模拟

用区域分裂有限体积法求解了三维Ｅｕｌｅｒ方程和Ｎａｖｉｅｒ－Ｓｔｏｋｅｓ方程。空间方向采用Ｒｏｅ平均算法，时间方向采用Ｒｕｎｇｅ－Ｋｕｔｔａ方法。对某飞航导弹的全弹身－进气道流场和某型号战斗机进气道内外流场进行了计算，得出了满意的结果。     

聚芳醚酮单体结构与反应活性的研究

利用从头算ＲＨＦ方法研究了聚芳醚酮单体４，４’－对苯二酚、４，４’－联苯二酚及４，４’－二氟苯酮。结果表明，它们的苯环皆存在一定的扭转，首次给出联苯二酚全优化结构，其苯环二面角为５１．８°，活性稍强于对苯二酚，但引入更多的链支化活特点，含联苯基聚芳醚醚酮的链支化比不含联苯基的ＰＥＥＫ严重，故前者结晶性差，反应机理及实验还表明：前者凝胶化的浓硫酸溶液中存在一种羰基被极化后的红色阴离子。     

守恒型双曲方程的中心差分TVD格式研究

研究了如何利用迎风格式的耗散性构造中心差分ＴＶＤ格式的方法，给 相应的定理，构造出新的耗散表达式。新格式既保留了二阶中心差分格式灵活方便的优点，又吸收了迎风格式耗散项比较精细的特点，同时具有ＴＶＤ性质，使得新格式具有较同的激波分辨率。     

Impact of symmetric gate-recess length on the DC and RF characteristics of InP HEMTs

We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(L_SD)unchanged,and obtained a group of devices with gate-recess length(L_recess)from 0.4μm to 0.8μm through process improvement.In order to suppress the influence of the kink effect,we have done SiN_X passivation treatment.The maximum saturation current density(ID_max)and maximum transconductance(g_m,max)increase as L_recess decreases to 0.4μm.At this time,the device shows ID_max=749.6 mA/mm at V_GS=0.2 V,V_DS=1.5 V,and g_m,max=1111 mS/mm at V_GS=?0.35 V,V_DS=1.5 V.Meanwhile,as L_recess increases,it causes parasitic capacitance C_gd and g_d to decrease,making f_max drastically increases.When L_recess=0.8μm,the device shows f_T=188 GHz and f_max=1112 GHz.     

Heterogeneous integration of InP HEMTs on quartz wafer using BCB bonding technology

Heterogeneous integrated InP high electron mobility transistors(HEMTs)on quartz wafers are fabricated successfully by using a reverse-grown InP epitaxial structure and benzocyclobutene(BCB)bonding technology.The channel of the new device is In_0.7Ga_0.3As,and the gate length is 100 nm.A maximum extrinsic transconductance gm,max of 855.5 mS/mm and a maximum drain current of 536.5 mA/mm are obtained.The current gain cutoff frequency is as high as 262 GHz and the maximum oscillation frequency reaches 288 GHz.In addition,a small signal equivalent circuit model of heterogeneous integration of InP HEMTs on quartz wafer is built to characterize device performance.     

Enhancement of fMAX of InP-based HEMTs by double-recessed offset gate process

A double-recessed offset gate process technology for InP-based high electron mobility transistors (HEMTs) has been developed in this paper. Single-recessed and double-recessed HEMTs with different gate offsets have been fabricated and characterized. Compared with single-recessed devices, the maximum drain-source current (I_D,max) and maximum extrinsic transconductance (g_m,max) of double-recessed devices decreased due to the increase in series resistances. However, in terms of RF performance, double-recessed HEMTs achieved higher maximum oscillation frequency (f_MAX) by reducing drain output conductance (g_ds) and drain to gate capacitance (C_gd). In addition, further improvement of f_MAX was observed by adjusting the gate offset of double-recessed devices. This can be explained by suppressing the ratio of C_gd to source to gate capacitance (C_gs) by extending drain-side recess length (L_rd). Compared with the single-recessed HEMTs, the f_MAX of double-recessed offset gate HEMTs was increased by about 20%.     

求解浅水波方程的熵相容格式

提出了一种求解浅水波方程组的熵相容格式．在熵稳定通量中添加特征速度差分绝对值的项来抵消解在跨过激波时所产生的熵增,从而实现熵相容．新的数值差分格式具有形式简单、计算效率高、无需添加任何的人工数值粘性的特点．数值算例充分说明了其显著的优点．利用新格式成功地模拟了不同类型溃坝问题的激波、稀疏波传播及溃坝两侧旋涡的形成,是求解浅水波方程组较为理想的方法.     

基于下变频和IQ解调的外差型相位敏感光时域反射技术的模式识别EI北大核心CSCD

基于模拟下变频器、数字IQ解调和反向传播(BP)神经网络,采用现场可编程门阵列结合数字信号处理器(FPGA+DSP)的数据采集和处理架构,提出了一种全嵌入式高信噪比(SNR)、高分辨率和低成本的外差型相位敏感光时域反射(Φ-OTDR)技术模式识别方法。针对外差型Φ-OTDR技术,使用DSP、FPGA及其外围硬件电路替代原有的GHz级高速采集卡和信号发生器,减小了系统的体积和成本。在此基础上,设计了基于时空域二维图提取形态学特征的方法,并采用BP神经网络进行分类识别;所提方法相对于传统的针对一维信号进行模式识别的方法误报率更低、识别率更高。实验结果表明,所设计的基于FPGA+DSP全嵌入式并行信号处理架构满足实时监测的要求,SNR高达12.43dB,事件识别准确率达到97.78%。     

Properties of Seamless W Sub-Micro Electrode Used for Phase Change Memory

In order to improve the reliability of C-RAM devices, a seamless sub-micro W heating electrode in diameter 260 nm is fabricated with standard 0.18 μm CMOS processing line. Then we successfully manufacture a chalcogenide random access memory device using this seamless sub-micro W heating electrode. The results show good electrical performance, e.g. the reset current of 1.3mA and the set/reset cycle up to 10^9 have been achieved.