衬底浮空的新型绝缘体上硅基横向功率器件分析

针对有机半导体领域的发展要求,报道了一种能够应用于有机半导体领域衬底浮空的新型SOI LDMOS(silicon on insulator lateral double-diffused metal oxide semiconductor)功率器件,不同于传统无机半导体中SOI LDMOS功率器件,该新型器件可以与绝缘...     

红外保护膜性能评估和分析

讨论红外保护膜的作用，分析和介绍保护膜的机械强度以及保护膜的外应力和内应力产生的破坏和影响，并提出了应对措施，探讨保护膜在恶劣环境下的光学性能，指出优化控制膜厚的重要性。     

Hardening measures for bipolar transistors against microwave-induced damage

In the present paper we study the influences of the bias voltage and the external components on the damage progress of a bipolar transistor induced by high-power microwaves. The mechanism is presented by analyzing the variation in the internal distribution of the temperature in the device. The findings show that the device becomes less vulnerable to damage with an increase in bias voltage. Both the series diode at the base and the relatively low series resistance at the emitter, Re, can obviously prolong the burnout time of the device. However, Re will aid damage to the device when the value is sufficiently high due to the fact that the highest hot spot shifts from the base-emitter junction to the base region. Moreover, the series resistance at the base Rb will weaken the capability of the device to withstand microwave damage.     

考虑工艺波动的RC互连树统计功耗

为了有效分析考虑工艺波动的RC互连树统计功耗,本文首先给出了考虑工艺波动的互连寄生参数和输入驱动点导纳矩的构建方法,然后,推导得出了互连功耗均值与标准差的表达式.计算结果表明,与目前广泛应用的Monte Carlo分析方法相比,采用本文方法得到的RC互连功耗均值误差小于4.36 %,标准差误差则小于6.68 %.结果显示,本文方法在确保精度的前提下大大缩短了仿真时间. 关键词： 工艺波动 RC互连')" href="#">RC互连 统计功耗     

考虑硅通孔的三维集成电路热传输解析模型

基于不考虑硅通孔的N层叠芯片的一维热传输解析模型,提出了硅通孔的等效热模型,获得了考虑硅通孔的三维集成电路热传输解析模型,并采用Matlab软件验证分析了硅通孔对三维集成电路热管理的影响.分析结果表明,硅通孔能有效改善三维集成电路的散热,硅通孔的间距增大将使三维集成电路的温升变大. 关键词： 三维集成电路 热管理 硅通孔 等效热模型     

Steady-state and transient electronic transport properties of β-(AlxGa1-x)2O3/Ga2O3 heterostructures: An ensemble Monte Carlo simulation

The steady-state and transient electron transport properties of $\beta $-(Al$_{x}$Ga$_{1-x}$)$_{2}$O$_{3}$/Ga$_{2}$O$_{3}$ heterostructures were investigated by Monte Carlo simulation with the classic three-valley model. In particular, the electronic band structures were acquired by first-principles calculations, which could provide precise parameters for calculating the transport properties of the two-dimensional electron gas (2DEG), and the quantization effect was considered in the $\varGamma $ valley with the five lowest subbands. Wave functions and energy eigenvalues were obtained by iteration of the Schrödinger-Poisson equations to calculate the 2DEG scattering rates with five main scattering mechanisms considered. The simulated low-field electron mobilities agree well with the experimental results, thus confirming the effectiveness of our models. The results show that the room temperature electron mobility of the $\beta $-(Al$_{0.188}$Ga$_{0.812}$)$_{2}$O$_{3}$/Ga$_{2}$O$_{3}$ heterostructure at 10 kV$ \cdot$cm$^{-1}$ is approximately 153.669 cm$^{2}\cdot$V$^{-1}\cdot$s$^{-1}$, and polar optical phonon scattering would have a significant impact on the mobility properties at this time. The region of negative differential mobility, overshoot of the transient electron velocity and negative diffusion coefficients are also observed when the electric field increases to the corresponding threshold value or even exceeds it. This work offers significant parameters for the $\beta$-(Al$_{x}$Ga$_{1-x}$)$_{2}$O$_{3}$/Ga$_{2}$O$_{3}$ heterostructure that may benefit the design of high-performance $\beta$-(Al$_{x}$Ga$_{1-x}$)$_{2}$O$_{3}$/Ga$_{2}$O$_{3}$ heterostructure-based devices.     

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.     

栅漏间表面外延层对4H-SiC功率MESFET击穿 特性的改善机理与结构优化

本文提出了一种带栅漏间表面p型外延层的新型MESFET结构并整合了能精确描述4H-SiC MESFET工作机理的数值模型,模型综合考虑了高场载流子饱和、雪崩碰撞离化以及电场调制等效应. 利用所建模型分析了表面外延层对器件沟道表面电场分布的改善作用,并采用突变结近似法对p型外延层参数与器件输出电流(I_ds)和击穿电压(V_B)的关系进行了研究.结果表明,通过在常规MESFET漏端处引入新的电场峰来降低栅极边缘的强电场峰并在栅漏之间的沟道表面引入p-n结内建电场进一步降低电场峰值,改善了表面电场沿电流方向的分布.通过与常规结构以及场板结构SiC MESFET的特性对比表明,本文提出的结构可以明显改善SiC MESFET的功率特性.此外,针对文中给定的器件结构,获得了优化的设计方案,选择p型外延层厚度为0.12 μupm,掺杂浓度为5× 10¹⁵ cm^-3,可使器件的V_B提高33%而保持I_ds基本不变.     

考虑通孔横向热传输效应的三维集成电路热分析

考虑横向热传输效应,构造一种包含通孔结构的叠层芯片三维热传输模型.在具体的工艺参数下验证叠层芯片层数、通孔密度、通孔直径和后端线互连层厚度对三维集成电路热传输的影响.结果显示,采用该模型仿真得到的各层芯片温升要低于不考虑横向热传输时所得到的温升,差异最大可达10%以上,并且集成度要求越高,其横向热传输效应的影响越明显.该模型更符合实际情况,能够更准确地分析三维集成电路的各层芯片温度.     

An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.