Channel temperature determination of a multifinger AlGaN/GaN high electron mobility transistor using a micro-Raman technique

Self-heating in a multifinger AlGaN/GaN high electron mobility transistor (HEMT) is investigated by micro-Raman spectroscopy. The device temperature is probed on the die as a function of applied bias. The operating temperature of the AlGaN/GaN HEMT is estimated from the calibration curve of a passively heated AlGaN/GaN structure. A linear increase of junction temperature is observed when direct current dissipated power is increased. When the power dissipation is 12.75 W at a drain voltage of 15 V, a peak temperature of 69.1°C is observed at the gate edge on the drain side of the central finger. The position of the highest temperature corresponds to the high-field region at the gate edge.     

Analysis and finite element simulation of electromagnetic heating in the nitride MOCVD reactor

Electromagnetic field distribution in the vertical metal organic chemical vapour deposition (MOCVD) reactor is simulated by using the finite element method (FEM). The effects of alternating current frequency, intensity, coil turn number and the distance between the coil turns on the distribution of the Joule heat are analysed separately, and their relations to the value of Joule heat are also investigated. The temperature distribution on the susceptor is also obtained. It is observed that the results of the simulation are in good agreement with previous measurements.     

Comparative study of different properties of GaN films grown on(0001) sapphire using high and low temperature AlN interlayers

Comparative study of high and low temperature AlN interlayers and their roles in the properties of GaN epilayers prepared by means of metal organic chemical vapour deposition on (0001) plane sapphire substrates is carried out by high resolution x-ray diffraction, photoluminescence and Raman spectroscopy. It is found that the crystalline quality of GaN epilayers is improved significantly by using the high temperature AlN interlayers, which prevent the threading dislocations from extending, especially for the edge type dislocation. The analysis results based on photoluminescence and Raman measurements demonstrate that there exist more compressive stress in GaN epilayers with high temperature AlN interlayers. The band edge emission energy increases from 3.423~eV to 3.438~eV and the frequency of Raman shift of $E_{2 }$(TO) moves from 571.3~cm$^{ - 1}$ to 572.9~cm$^{ - 1}$ when the temperature of AlN interlayers increases from 700~$^{\circ}$C to 1050~$^{\circ}$C. It is believed that the temperature of AlN interlayers effectively determines the size, the density and the coalescence rate of the islands, and the high temperature AlN interlayers provide large size and low density islands for GaN epilayer growth and the threading dislocations are bent and interactive easily. Due to the threading dislocation reduction in GaN epilayers with high temperature AlN interlayers, the approaches of strain relaxation reduce drastically, and thus the compressive stress in GaN epilayers with high temperature AlN interlayers is high compared with that in GaN epilayers with low temperature AlN interlayers.     

Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor

This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.     

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.     

Influence of dislocations in the GaN layer on the electrical properties of an AlGaN/GaN heterostructure

This paper reports on a comparative study of the spatial distributions of the electrical, optical, and structural properties in an AlGaN/GaN heterostructure. Edge dislocation density in the GaN template layer is shown to decrease in the regions of the wafer where the heterostructure sheet resistance increases and the GaN photoluminescence band-edge energy peak shifts to a high wavelength. This phenomenon is found to be attributed to the local compressive strain surrounding edge dislocation, which will generate a local piezoelectric polarization field in the GaN layer in the opposite direction to the piezoelectric polarization field in the AlGaN layer and thus help to increase the two-dimensional electron gas concentration.     

Study on the recovery of NBTI of ultra-deep sub-micro MOSFETs

Taking the actual operating condition of complementary metal oxide semiconductor (CMOS) circuit into account, conventional direct current (DC) stress study on negative bias temperature instability (NBTI) neglects the detrapping of oxide positive charges and the recovery of interface states under the `low' state of p-channel metal oxide semiconductor field effect transistors (MOSFETs) inverter operation. In this paper we have studied the degradation and recovery of NBTI under alternating stress, and presented a possible recovery mechanism. The three stages of recovery mechanism under positive bias are fast recovery, slow recovery and recovery saturation.     

A compact I－V model for lightly-doped-drain MOSFETs

A novel model for lightly-doped-drain (LDD) MOSFETs is proposed, which utilizes the empirical hyperbolic tangent function to describe the I－V characteristics. The model includes the strong inversion and subthreshold mechanism, and shows a good prediction for submicron LDD MOSFET. Moreover, the model requires low computation time consumption and is suitable for design of MOSFETs devices and circuits.     

金红石TiO_2中本征缺陷扩散性质的第一性原理计算

基于密度泛函理论的爬坡弹性带方法,对金红石相二氧化钛晶体中钛间隙、钛空位、氧间隙、氧空位4种本征缺陷的扩散特征进行了研究.对比4种本征缺陷在晶格内部沿不同扩散路径的过渡态势垒后发现,缺陷扩散过程呈现出明显的各向异性.其中,钛间隙和氧间隙沿[001]方向具有最小的扩散势垒路径,激活能分别为0.505 eV和0.859 eV;氧空位和钛空位的势垒最小的扩散路径分别沿[110]方向和[111]方向,激活能分别为0.735 eV和2.375 eV.