High temperature characteristics of AlGaN/GaN high electron mobility transistors

Direct current (DC) and pulsed measurements are performed to determine the degradation mechanisms of AlGaN/GaN high electron mobility transistors (HEMTs) under high temperature. The degradation of the DC characteristics is mainly attributed to the reduction in the density and the mobility of the two-dimensional electron gas (2DEG). The pulsed measurements indicate that the trap assisted tunneling is the dominant gate leakage mechanism in the temperature range of interest. The traps in the barrier layer become active as the temperature increases, which is conducive to the electron tunneling between the gate and the channel. The enhancement of the tunneling results in the weakening of the current collapse effects, as the electrons trapped by the barrier traps can escape more easily at the higher temperature.     

Enhancement-mode AlGaN/GaN high electronic mobility transistors with thin barrier

An enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMTs) was fabricated with 15-nm AlGaN barrier layer. E-mode operation was achieved by using fluorine plasma treatment and post-gate rapid thermal annealing. The thin barrier depletion-HEMTs with a threshold voltage typically around --1.7 V, which is higher than that of the 22-nm barrier depletion-mode HEMTs (--3.5 V). Therefore, the thin barrier is emerging as an excellent candidate to realize the enhancement-mode operation. With 0.6-μ m gate length, the devices treated by fluorine plasma for 150-W RF power at 150 s exhibited a threshold voltage of 1.3 V. The maximum drain current and maximum transconductance are 300 mA/mm, and 177 mS/mm, respectively. Compared with the 22-nm barrier E-mode devices, V_T of the thin barrier HEMTs is much more stable under the gate step-stress.     

Investigation of AlGaN/GaN fluorine plasma treatment enhancement-mode high electronic mobility transistors by frequency-dependent capacitance and conductance analysis

This paper reports fluorine plasma treatment enhancement-mode HEMTs (high electronic mobility transistors) EHEMTs and conventional depletion-mode HEMTs DHEMTs fabricated on one wafer using separate litho-photography technology. It finds that fluorine plasma etches the AlGaN at a slow rate by capacitance--voltage measurement. Using capacitance--frequency measurement, it finds one type of trap in conventional DHEMTs with τ_T=(0.5-6) ms and D_T= (1 - 5) × 10¹³ cm^-2·eV^-1. Two types of trap are found in fluorine plasma treatment EHEMTs, fast with τ_T(f)=(0.2-2) μs and slow with τ_T(s)=(0.5-6) ms. The density of trap states evaluated on the EHEMTs is D_T(f)=(1 - 3) × 10¹² cm^-2·eV^-1 and D_T(s)=(2 - 6) × 10¹² cm^-2·eV^-1 for the fast and slow traps, respectively. The result shows that the fluorine plasma treatment reduces the slow trap density by about one order, but introduces a new type of fast trap. The slow trap is suggested to be a surface trap, related to the gate leakage current.     

Phonon Limited Electron Mobility in Germanium FinFETs:Fin Direction Dependence

We investigate the phonon limited electron mobility in germanium(Ge) fin field-effect transistors(FinFETs)with fin rotating within(001),(110),and(111)-oriented wafers. The coupled Schrodinger-Poisson equations are solved self-consistently to calculate the electronic structures for the two-dimensional electron gas, and Fermi's golden rule is used to calculate the phonon scattering rate. It is concluded that the intra-valley acoustic phonon scattering is the dominant mechanism limiting the electron mobility in Ge FinFETs. The phonon limited electron motilities are influenced by wafer orientation, channel direction, in thickness Wfin, and inversion charge density Ninv. With the fixed Wfin, fin directions of(110),(112) and(110) within(001),(110), and(111)-oriented wafers provide the maximum values of electron mobility. The optimized for mobility is also dependent on wafer orientation and channel direction. As Ninv, increases, phonon limited mobility degrades, which is attributed to electron repopulation from a higher mobility valley to a lower mobility valley as Ninv increases.     

基于锡组分和双轴张应力调控的临界带隙应变Ge_(1-x)Sn_x能带特性与迁移率计算

能带工程通过改变材料的能带结构可以显著提升其电学和光学性质,已广泛应用于半导体材料的改性研究.双轴张应力和Sn组分共同作用下的Ge_(1-x)Sn_x合金,不仅可以解决直接带隙转变所需高Sn组分带来的工艺难题,而且载流子迁移率会显著提升,在单片光电集成领域有很好的应用前景.根据形变势理论,分析了(001)面双轴张应变Ge_(1-x)Sn_x的带隙转变条件,并给出了在带隙转变临界点Sn组分和双轴张应力的关系;采用8κ·p方法,得到了临界带隙双轴张应变Ge_(1-x)Sn_x在布里渊区中心点附近的能带结构,进而计算得到电子与空穴有效质量;基于载流子散射模型,计算了电子与空穴迁移率.计算结果表明:较低Sn组分和双轴张应力的组合即可得到直接带隙Ge_(1-x)Sn_x合金,且直接带隙宽度随着应力的增大而减小;临界带隙双轴张应变Ge_(1-x)Sn_x具有极高的电子迁移率,空穴迁移率在较小应力作用下即可显著提升.考虑工艺实现难度和材料性能两个方面,可以选择4%Sn组分与1.2 GPa双轴张应力或3%Sn组分与1.5 GPa双轴张应力的组合用于高速器件和光电器件的设计.     

Characteristics and threshold voltage model of GaN-based FinFET with recessed gate

In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value and positive shift of threshold voltage. Moreover, with the fin width of the recessed-gate FinFETs increasing, the variations of both threshold voltage and the transconductance increase. Next, transfer characteristics of the recessed-gate FinFETs with different fin widths and recessed-gate depths are simulated by Silvaco software. The relationship between the threshold voltage and the AlGaN layer thickness has been investigated. The simulation results indicate that the slope of threshold voltage variation reduces with the fin width decreasing. Finally, a simplified threshold voltage model for recessed-gate FinFET is established,which agrees with both the experimental results and simulation results.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

高温AlN插入层对AlGaN/GaN异质结材料和HEMTs器件电学特性的影响

研究了在GaN缓冲层中插入40 nm厚高温AlN层的GaN外延层和AlGaN/GaN异质结材料, AlN插入层可以增加GaN层的面内压应力并提高AlGaN/GaN高电子迁移率晶体管（HEMTs）的电学特性. 在精确测量布拉格衍射角的基础上定量计算了压应力的大小. 增加的压应力一方面通过增强GaN层的压电极化电场, 提高了AlGaN/GaN异质结二维电子气（2DEG）面密度, 另一方面使AlGaN势垒层对2DEG面密度产生的两方面影响相互抵消. 同时, 这种AlN插入层的采用降低了GaN与AlGaN层之间的 关键词： 高温AlN插入层 AlGaN/GaN异质结 二维电子气 应力     

60Co γ射线辐射对AlGaN/GaN HEMT器件的影响

采用60 Co γ射线辐射源对非钝化保护的AlGaN/GaN高电子迁移率晶体管(HEMT)器件进行了1 Mrad(Si)的总剂量辐射,实验发现辐射累积剂量越大,器件尺寸越小,器件饱和漏电流和跨导下降越明显,同时辐射后器件栅泄漏电流明显增大,而阈值电压变化很小. 对辐射前后器件的沟道串联电阻和阈值电压变化的分析表明,辐射感生表面态负电荷的产生是造成AlGaN/GaN HEMT器件电特性退化的主要原因之一.     

AlGaN/GaN场板结构高电子迁移率晶体管的场板尺寸优化分析

对不同场板尺寸的AlGaN/GaN 场板结构高电子迁移率晶体管进行了研究,建立简化模型分析场板长度对沟道电场分布的影响.结果表明,调整钝化层厚度和场板长度都可以调制沟道电场的分布形状,当场板长度较小时,随着长度的增大器件击穿电压随之增加,而当长度增大到一定程度后器件击穿电压不再增加.通过优化场板长度,器件击穿电压提高了64%,且实验结果与模拟结果相符. 关键词： AlGaN/GaN 击穿电压 场板长度