The role of hydrogen in negative bias temperature instability of pMOSFET

The NBTI degradation phenomenon and the role of hydrogen during NBT stress are presented in this paper. It is found that PBT stress can recover a fraction of V_th shift induced by NBTI. However, this recovery is unstable. The original degradation reappears soon after reapplication of the NBT stress condition. Hydrogen-related species play a key role during a device's NBT degradation. Experimental results show that the diffusion species are neutral, they repassivate Si dangling bond which is independent of the gate voltage polarity. In addition to the diffusion towards gate oxide, hydrogen diffusion to Si-substrate must be taken into account for it also has important influence on device degradation during NBT stress.     

GaN-based heterostructures: electric--static equilibrium and boundary conditions

In the GaN-based heterostructures, this paper reports that the strong electric fields induced by polarization effects at the structure boundaries complicate the electric--static equilibrium and the boundary conditions. The basic requirements of electric--static equilibrium for the heterostructure systems are discussed first, and it is deduced that in the application of the coupled Schr\"{o}dinger--Poisson model to the heterostructures of electric--static equilibrium state, zero external electric field guarantees the overall electric neutrality, and there is no need to introduce the charge balance equation. Then the relation between the screening of the polar charges in GaN-based heterostructures and the possible boundary conditions of the Poisson equation is analysed, it is shown that the various boundary conditions are equivalent to each other, and the surface charge, which can be used in studying the screening of the polar charges, can be precisely solved even if only the conduction band energy is correctly known at the surface. Finally, through the calculations on an AlGaN/GaN heterostructure with typical structure parameters by the coupled Schr\"{o}dinger--Poisson model under the various boundary conditions, the correctness of the above analyses are validated.     

New aspects of HCI test for ultra-short channel n-MOSFET devices

Hot carriers injection (HCI) tests for ultra-short channel n-MOSFET devices were studied. The experimental data of short channel devices (75--90\,nm), which does not fit formal degradation power law well, will bring severe error in lifetime prediction. This phenomenon usually happens under high drain voltage ($V_{\rm d}$) stress condition. A new model was presented to fit the degradation curve better. It was observed that the peak of the substrate current under low drain voltage stress cannot be found in ultra-short channel device. Devices with different channel lengths were studied under different $V_{\rm d}$ stresses in order to understand the relations between peak of substrate current ($I_{\rm sub}$) and channel length/stress voltage.     

Critical area computation for real defects and arbitrary conductor shapes

In current critical area models, it is generally assumed the defect outlines are circular and the conductors to be rectangle or the merger of rectangles. However, real defects and conductors associated with optimal layout design exhibit a great variety of shapes. Based on mathematical morphology, a new critical area model is presented, which can be used to estimate the critical area of short circuit, open circuit and pinhole. Based on the new model, the efficient validity check algorithms are explored to extract critical areas of short circuit, open circuit and pinhole from layouts. The results of experiment on an approximate layout of ${4\times 4}$ shifts register show that the new model predicts the critical areas accurately. These results suggest that the proposed model and algorithm could provide new approaches for yield prediction.     

Temperature dependence of Hall electron density of GaN-based heterostructures

The theoretic calculation and analysis of the temperature dependence of Hall electron density of a sample AlGaN/GaN heterostructure has been carried out in the temperature range from 77 to 300K. The densities of the two-dimensional electron gas and the bulk electrons are solved by self-consistent calculation of one-dimensional Schr?dinger and Poisson equations at different temperatures, which allow for the variation of energy gap and structure strain, and are used for evaluation of the temperature dependence of Hall electron density. The calculated Hall electron density agrees with the measured one quite well with the appropriate bulk mobility data. Analysis revealed that for the temperature range considered, even in the heterostructures with a small bulk conductance the factors that determine the Hall mobility and electron density could be of different sources, and not just the two-dimensional electron gas as generally supposed.     

应力导致的薄栅氧化层漏电流瞬态特性研究

分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性.在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同.热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性.研究结果表明:热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没.利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱.     

HOT-CARRIER GENERATION MECHANISM AND HOT-CARRIER EFFECT IMMUNITY IN DEEP-SUB-MICRON GROOVED-GATE PMOSFETS

Based on the hydrodynamic energy transport model, immunity from the hot-carrier effect in deep-sub-micron grooved-gate p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) is analysed. The results show that hot carriers generated in grooved-gate PMOSFETs are much smaller than those in planar ones, especially for the case of channel lengths lying in the deep-sub-micron and super deep-sub-micron regions. Then, the hot-carrier generation mechanism and the reason why grooved-gate MOS devices can suppress the hot-carrier effect are studied from the viewpoint of physical mechanisms occurring in devices. It is found that the highest hot-carrier generating rate is at a medium gate bias voltage in three stress areas, similar to conventional planar devices. In deep-sub-micron grooved-gate PMOSFETs, the hot-carrier injection gate current is still composed mainly of the hot-electron injection current, and the hole injection current becomes dominant only at an extremely high gate voltage. In order to investigate other influences of the hot-carrier effect on the device characteristics, the degradation of the device performance is studied for both grooved-gate and planar devices at different interface states. The results show that the drift of the device electrical performance induced by the interface states in grooved-gate PMOSFETs is far larger than that in planar devices.     

Effect of Channel Length and Width on NBTI in Ultra Deep Sub-Micron PMOSFETs

The effects of channel length and width on the degradation of negative bias temperature instability （NBTI） are studied. With the channel length decreasing, the NBTI degradation increases. As tile channel edges have more damage and latent damage for the process reasons, the device can be divided into three parts： the gate and source overlap region, the middle channel region, and the gate and drain overlap region. When the NBTI stress is applied, the non-uniform distribution of the generated defects in the three parts will be generated due to the inhomogeneous degradation. With tile decreasing channel length, tile channel edge regions will take up a larger ratio to the middle channel region and the degradation of NBTI is enhanced. The channel width also plays an important role in the degradation of NBTI. There is an inflection point during the decreasing channel width. There are two particular factors： the lower vertical electric field effect for the thicker gate oxide thickness of the sha/low trench isolation （STI） edge and the STI mechanical stress effecting on the NBTI degradation. The former reduces and the latter intensifies the degradation. Under the mutual compromise of the both factors, when the effect of the STI mechanical stress starts to prevail over the lower vertical electric field effect with the channel width decreasing, the inflection point comes into being.     

Improved mobility of AIGaN channel heterojunction material using an AIGaN/GaN composite buffer layer

The quality of an A1GaN channel heterojunction on a sapphire substrate is massively improved by using an A1- GaN/GaN composite buffer layer. We demonstrate an A10.4Gao.6N/AI0.18Ga0.82N heterojunction with a state-of-the-art mobility of 815 cm2/（V.s） and a sheet resistance of 890Ω/口 under room temperature. The crystalline quality and the electrical properties of the A1GaN heterojunction material are analyzed by atomic force microscopy, high-resolution X-ray diffraction, and van der Pauw Hall and capacitance-voltage （C-V） measurements. The results indicate that the improved electrical properties should derive from the reduced surface roughness and low dislocation density.