排序方式: 共有54条查询结果,搜索用时 15 毫秒
31.
Highly arsenic-doped Si-on-insulator (SOI) substrate incorporated with buried MoSi2 layers is fabricated aiming at decreasing the collector series resistance of SiGe heterojunction bipolar transistors (HBTs) on SOI, thereby enhancing cutoff frequency (fT) performance and increasing the maximum value of fT (fTMAX ). The .fT performance at medium current is enhanced and current required for fT = 15 GHz is reduced by half The value of fTMAX is improved by 30%. 相似文献
32.
We investigate the effect of chemicals on chemical mechanical polishing (CMP) of glass substrates. Ceria slurry in an ultra-low concentration of 0.25 wt. % is used and characterized by scanning electron microscopy. Three typical molecules, i.e. acetic acid, citric acid and sodium acrylic polymer, are adopted to investigate the effect on CMP performance in terms of material removal rate (MRR) and surface quality. The addition of sodium acrylic polymer shows the highest MRR as well as the best surface by atomic force microscopy after CMP, while the addition of citric acid shows the worst performance. These results reveal a mechanism that a long-chain molecule without any branches rather than small molecules and common molecules with ramose abundant-electron groups is better for the dispersion of the slurry and thus better for the CMP process. 相似文献
33.
Ge1Sb2Te4 Based Chalcogenide Random Access Memory Array Fabricated by 0.18-μm CMOS Technology
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Ge1Sb2Te4-based chalcogenide random access memory array, with a tungsten heating electrode of 260hm in diameter, is fabricated by 0.18-μm CMOS technology. Electrical performance of the device, as web as physical and electrical properties of GelSb2 Te4 thin film, is characterized. SET and RESET programming currents are 1.6 and 4.1 mA, respectively, when pulse width is 100 ns. Both the values are larger than those of the Ge2Sb2 Tesbased ones with the same structure and contact size. Endurance up to 106 cycles with a resistance ratio of about 100 has been achieved. 相似文献
34.
A new industrial method has been developed to produce polydisperse spherical colloidal silica particles with a very broad particle size,ranging from 20-95 nm.The process uses a reactor in which the original seed solution is heated to 100 ℃,and then active silicic acid and the seed solution are titrated to the reactor continuously with a constant rate.The original seeds and the titrated seeds in the reactor will go through different particle growth cycles to form different particle sizes.Both the particles' size distribution and morphology have been characterized by dynamic light scattering(DLS)and the focus ion beam(FIB) system.In addition,the as-prepared polydisperse colloidal silica particle in the application of sapphire wafer's chemical mechanical polishing(CMP) process has been tested.The material removal rate(MRR) of this kind of abrasive has been tested and verified to be much faster than traditional monodisperse silica particles.Finally,the mechanism of sapphire CMP process by this kind of polydisperse silica particles has been investigated to explore the reasons for the high polishing rate. 相似文献
35.
Ultra-thin and near-fully relaxed SiCe substrate is fabricated using a modified Ce condensation technique, and then a 25-nm-thiek biaxially tensile strained-Si with a low rms roughness is epitaxially deposited on a SiGe- on-Insulator (SGOI) substrate by ultra high vacuum chemical vapor deposition (UHVCVD). High-Resolution cross-sectional transmission electron microscope (HR-XTEM) observations reveal that the strained-Si/SiGe layer is dislocation-free and the atoms at the interface are well aligned. Furthermore, secondary ion mass spectrometry (SIMS) results show a sharp interface between layers and a uniform distribution of Ge in the SiCe layer. One percent in-plane tensile strain in the strained-Si layer is confirmed by ultraviolet (UV) Raman spectra, and the stress maintained even after a 30-s rapid thermal annealing (RTA) process at 1000℃. According to those results, devices based on strained-Si are expected to have a better performance than the conventional ones. 相似文献
36.
CdS是一种直接带隙半导体,室温下其禁带宽度约为2.4eV,是一种良好的太阳能电池窗口层材料和过渡层材料.分别以CdCl2和(NH2)2CS作为镉源和硫源,用化学淀积法在玻璃上生长CdS纳米薄膜,考察了Cd2+浓度、淀积温度、淀积时间以及溶液pH值对CdS成膜的影响.紫外可见光吸收谱和荧光光谱的结果表明,在样品的制备过程中,通过改变反应条件如化学试剂的浓度、加热温度、加热时间等来控制薄膜中颗粒的尺寸大小,随着反应温度的逐渐降低或反应时间的减少等可以使得到的CdS纳米晶薄膜中晶粒尺寸逐渐减小,带隙增加;镉离子浓度越小或氨水浓度越大,所得CdS纳米晶薄膜带隙越大. 相似文献
37.
Nanoscale Tapered Pt Bottom Electrode Fabricated by FIB for Low Power and Highly Stable Operations of Phase Change Memory
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Phase change random access memory (PC-RAM) based on Si2Sb2Te5 with a Pt tapered heating electrode (Pt-THE), which is fabricated using a focus ion beam (FIB), is investigated. Compared with the tungsten electrode, the Pt-THE facilitates the temperature rise in phase change material, which causes the decrease of reset voltage from 3.6 to 2.7 V. The programming region of the cell with the Pt-THE is smaller than that of the cell with a cylindrical tungsten heating electrode. The improved performance of the PC-RAM with a Pt-THE is attributed to the higher resistivity and lower thermal conductivity of the Pt electrode, and the reduction of the programming region, which is also verified by thermal simulation. 相似文献
38.
纳米球刻蚀法制备的二维有序的CdS纳米阵列及其光学性质的研究 总被引:1,自引:0,他引:1
采用纳米球刻蚀(nanosphere lithography)技术,以自组装的聚苯乙烯纳米小球(polystyrene,PS小球)的单层膜为掩模,制备出二维有序的CdS纳米阵列.利用扫描电子显微镜(SEM)对样品结构进行了表征,用紫外—可见分光光度计对样品光学性质进行了分析.结果表明:制备的二维CdS纳米阵列是高度有序的,且与作为掩模的纳米小球的原始尺寸及排布结构一致;禁带宽度为2.60eV,相对于体材料的2.42eV,向短波长蓝移了0.18eV,表现出CdS材料在纳米结构点阵中的量子尺寸效应;CdS纳米关键词:纳米球刻蚀二维CdS纳米有序阵列 相似文献
39.
A 0.18-μm 3.3 V 16 k Bits 1RIT Phase Change Random Access Memory (PCRAM) Chip 总被引:1,自引:0,他引:1
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Using standard 0.18-μm CMOS process and the special platform for S-inch phase change random access memory (PCRAM), the first Chinese 16k bits PCRAM chip has been successfully achieved. A 1RIT structure has been designed for low voltage drop and low cost compared to the 1RlD structure and the BJT-switch structure. Full integration of the 16k bits PCRAM chip, including memory cell, array structure, critical circuit module, and physical layout, has been designed and verified. The critical integration technology of the phase change material (PCM) fabrication and the standard CMOS process has been solved. Test results about PCM in a large-scale array have been generated for the next research of PCRAM chip. 相似文献
40.