总剂量辐射环境中的静态随机存储器功能失效模式研究

本文对静态随机存储器 (SRAM) 总剂量辐射引起的功能失效进行了六种不同测试图形下的测试. 利用不同测试图形覆盖的出错模式不同, 通过对比一定累积剂量下同一器件不同测试图形测试结果的差异, 以及对失效存储单元单独进行测试, 研究了总剂量辐照引起的SRAM器件功能失效模式. 研究表明: 器件的功能失效模式为数据保存错误 (Data retention fault) 且数据保存时间具有离散性, 引起数据保存错误的SRAM功能模块为存储单元. 通过对存储单元建立简化的等效电路图, 分析了造成存储单元数据保存错误以及保存时间离散性的原因, 并讨论了该失效模式对SRAM总剂量辐射功能测试方法的影响. 关键词： 静态随机存储器 功能失效 测试图形 数据保存错误     

中带电压法分离栅控横向pnp双极晶体管辐照感生缺

设计并制作了一种新型双极测试结构,即在常规横向pnp双极晶体管基区表面氧化层上淀积一栅电极,通过扫描栅极所加电压,获得漏极(集电极)电流随栅极电压的变化特性,利用中带电压法分离栅控横向pnp双极晶体管 在辐照过程中感生的氧化物陷阱电荷和界面陷阱电荷.本文对设计的晶体管测试结构和采用 的测试方法做了具体介绍.     

Pattern imprinting in deep sub-micron static random access memories induced by total dose irradiation

Pattern imprinting in deep sub-micron static random access memories(SRAMs) during total dose irradiation is investigated in detail. As the dose accumulates, the data pattern of memory cells loading during irradiation is gradually imprinted on their background data pattern. We build a relationship between the memory cell’s static noise margin(SNM) and the background data, and study the influence of irradiation on the probability density function of ?SNM, which is the difference between two data sides’ SNMs, to discuss the reason for pattern imprinting. Finally, we demonstrate that, for micron and deep sub-micron devices, the mechanism of pattern imprinting is the bias-dependent threshold shift of the transistor, but for a deep sub-micron device the shift results from charge trapping in the shallow trench isolation(STI) oxide rather than from the gate oxide of the micron-device.     

Enhanced Total Ionizing Dose Hardness of Deep Sub-Micron Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors by Applying Larger Back-Gate Voltage Stress

Owing to the fifll isolation and minimization of the silicon active volume, silicon-on-insulator （SOI） tech- nology has better resistance against transient ionizing effects like single event effects （SEE） or latch up.However, the total ionizing dose （TID） irradiation responses of SOI transistors are more complex than bulk-silicon devices. In addition to the gate and par- asitic field leakage current, which are common to SOI and bulk-silicon devices, irradiation induced charges trapped in the SOI buried oxide （BOX） can also affect SOI device performance. Typically, there is a par- asitic edge transistor in the back-gate of SOI devices paralleled with the main transistor, which is formed by the corner region of the silicon island. Due to the high electric field induced by the back-gate voltage at the corner of the silicon island, the threshold of the parasitic edge transistor is lower than the main transistor, resulting in a sub-threshold hump in the transfer characteristic of the back-gate transistor. Even though the threshold of the parasitic edge tran- sistor is lower than the main transistor, it is still larger than zero, which has no effect on the front- gate of devices. However, the sub-threshold hump in the back-gate is the ＇Achilles heel＇ for total dose responses of deep sub-micron SOI n-type metal-oxide- semiconductor field-effect transistors （MOSFETs） iso- lated by shallow trench isolation （STI）. As reported in Refs., the threshold of the parasitic edge transis- tor is negative shifted by radiation-induced charges trapped in STI, leading to off-state leakage in the front-gate of devices.