High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

"十一五"规划国家级重点通信项目

《信息产业科技发展“十一五”规划》提出设立部分重大项目,力争实现重点突破,形成一批具有自主知识产权的核心技术和创新产品,打造较为完整的产业链,形成世界一流的产业群。这其中,与通信相关的重点项目主要有:宽带无线移动通信、下一代网络、家庭网络、智能终端、数字电视等。本部分将对我国在以上领域的现状、项目的具体内容和目标、实现这些目标的具体计划以及相关厂商在各领域的努力和成绩进行介绍。     

A novel compact ring dual-mode filter with adjustable second-passband for dual-band applications

In this letter, a novel compact ring dual-mode with adjustable second-passband for dual-band applications are presented. A ring resonator with two different geometric dimensions are derived and designed to have identical fundamental and the first higher-order resonant frequencies, and to establish appropriate couplings in the structure. Moreover, the proposed filter has smaller size as compared with the basic topology of stopband filters and stepped-impedance-resonator (SIR) filters. The measured filter performance is in good agreement with the simulated response.     

Whispering-gallery-like modes in square resonators

The mode frequencies and field distributions of whispering-gallery (WG)-like modes of square resonators are obtained analytically, which agree very well with the numerical results calculated by the FDTD technique and Pade approximation method. In the analysis, a perfect electric wall for the transverse magnetic mode or perfect magnetic wall for the transverse electric mode is assumed at the diagonals of the square resonators, which not only provides the transverse mode confinement, but also requires the longitudinal mode number to be an even integer. The WG-like modes of square resonators are nondegenerate modes with high-quality factors, which make them suitable for fabricating single-mode low-threshold semiconductor microcavity lasers.     

MAX3100在80C196串口扩展中的应用

介绍采用新型的UART器件MAX3100为Intel单片机80C196扩展串口，给出了硬件设计和软件编程，并对关键技术进行了说明。     

Filter matrix estimation in automated DNA sequencing

In four-color fluorescence-based automated DNA sequencing, a 4×4 filter matrix parameterizes the relationship between the dye-intensity signals of interest and the data collected by an optical imaging system. The filter matrix is important because the estimated DNA sequence is based on the dye intensities that can only be recovered via inversion of the matrix. Here, the authors present a calibration method for the estimation of the columns of this matrix, using data generated through a special experiment in which DNA samples are labeled with only one fluorescent dye at a time. Simulations and applications of the method to real data are provided, with promising results     

Interfacial reactions in In-Sn/Ni couples and phase equilibria of the In-Sn-Ni system

The In-Sn-Ni alloys of various compositions were prepared and annealed at 160°C and 240°C. No ternary compounds were found; however, most of the binary compounds had extensive ternary solubility. There was a continuous solid solution between the Ni₃Sn phase and Ni₃In phase. The Sn-In/Ni couples, made of Sn-In alloys with various compositions, were reacted at 160°C and 240°C and formed only one compound for all the Sn-In alloys/Ni couples reacted up to 8 h. At 240°C, Ni₂₈In₇₂ phase formed in the couples made with pure indium, In-10at.%Sn and In-11at.%Sn alloys, while Ni₃Sn₄ phase formed in the couples made of alloys with compositions varied from pure Sn to In-12at.%Sn. At 160°C, except in the In/Ni couple, Ni₃Sn₄ formed by interfacial reaction.     

Analysis of multiple FSS screens of unequal periodicity using an efficient cascading technique

In this paper, we present an efficient cascading procedure for analyzing frequency selective surface (FSS) systems consisting of multiple FSS screens of unequal periodicity embedded in multiple dielectric layers. In this procedure, we first find a global period for the FSS system by studying the composite in its entirety. Next, we compute the scattering matrix [S] of each of the FSS subsystems for the global Floquet harmonics by applying a relationship we establish that maps the [S] matrix of the subsystem for the individual Floquet harmonics to that for the global harmonics. This mapping-cum-filling process substantially reduces the effort needed to compute the [S] matrix of a subsystem. Finally, we compute the [S] of the entire system by applying a modified cascading formulation, in which one matrix inversion step is eliminated, resulting in a reduction in the total computing resource requirement as well as time. Two numerical examples are given to illustrate the efficiency and effectiveness of the technique.