Condensation of all-cis-tetraphenylcyclotetrasiloxanetetraol in ammonia: new method for preparation of ladder-like polyphenylsilsesquioxanes

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Atmospheric chemistry of diazomethane – an experimental and theoretical study

The kinetics of the O₃, OH and NO₃ radical reactions with diazomethane were studied in smog chamber experiments employing long-path FTIR and PTR-ToF-MS detection. The rate coefficients were determined to be k _CH2NN+O3?=?(3.2?±?0.4)?×?10^?17 and k _CH2NN+OH?=?(1.68?±?0.12)?×?10^?10 cm³ molecule^?1 s^?1 at 295?±?3?K and 1013?±?30 hPa, whereas the CH₂NN?+?NO₃ reaction was too fast to be determined in the static smog chamber experiments. Formaldehyde was the sole product observed in all the reactions. The experimental results are supported by CCSD(T*)-F12a/aug-cc-pVTZ//M062X/aug-cc-pVTZ calculations showing the reactions to proceed exclusively via addition to the carbon atom. The atmospheric fate of diazomethane is discussed.     

Periodic Néel skyrmion transport

In this work, we have used the MuMax3 software to simulate devices consisting of a ferromagnetic thin film placed over a heavy metal thin film. The devices are two interconnected partial-disks where a Néel domain wall is formed in the disks junction. In our simulations we investigate devices with disk radius $r=50$ nm and different distance d between the disks centers (from $d=12$ nm to $d=2R=100$ nm). By applying strong sinusoidal external magnetic fields, we find a mechanism able to create, annihilate and even manipulate a skyrmion in each side of the device. This mechanism is discussed in terms of interactions between skyrmion and domain wall. The Néel domain wall formed in the center of the device interacts with the Néel skyrmion, leading to a process of transporting a skyrmion from one disk to the other periodically. Our results have relevance for potential applications in spintronics such as logical devices.     

Reliable eye-diagram analysis of data links via device macromodels

This paper addresses the impact of device macromodels on the accuracy of signal integrity and performance predictions for critical digital interconnecting systems. It exploits nonlinear parametric models for both single-ended and differential devices, including the effects of power supply fluctuations and receiver bit detection. The analysis demonstrates that the use of well-designed macromodels dramatically speeds up the simulation as well it preserves timing accuracy even for long bit sequences.     

PowerNap: an efficient power management scheme for mobile devices

We present PowerNap, an OS power management scheme, which can significantly improve the battery life of mobile devices. The key feature of PowerNap is the skipping of the periodic system timer ticks associated with the operating system. On an idle device, this modification increases the time between successive timer interrupts and enables us to put the processor/system into a more efficient low power state. This saves the energy consumed by workless timer interrupts and the excess energy consumed by the processor in less efficient low power states. PowerNap is tightly integrated with the kernel and is designed for optimal control of the latency and energy associated with transitioning in and out of the low power states. We describe an implementation of PowerNap and its impact on system software. Experiments with IBM's WatchPad verify the ability of PowerNap to extend battery life. An analytical model that quantifies the ability of the scheme to reduce power is also presented. The model is in good agreement with experimental results. We apply the model to small form-factor devices which use processors that have a PowerDown state. In such devices, PowerNap may extend battery life by more than 42 percent for small processor workloads and for background power levels below 10 mW.     

Performance study of iSCSI-based storage subsystems

iISCSI is emerging as an end-to-end protocol for transporting storage I/O block data over IP networks. By exploiting the ubiquitous Internet infrastructure, iSCSI greatly facilitates remote storage, remote backup, and data mirroring. This article evaluates the performance of two typical iSCSI storage subsystems by measuring and analyzing block-level I/O access performance and file-level access performance. In the file-level performance study, we compare file access performance in an NAS scheme with that in an iSCSI-based SAN scheme. Our test results show that Gigabit Ethernet-based iSCSI can reach very high bandwidth, close to that of a direct FC disk access in block I/O access. However, when the iSCSI traverses through longer distance, throughput relies heavily on the available bandwidth between the initiator and the target. On the other hand, the file-level performance shows that iSCSI-based file access (SAN scheme) provides higher performance than using NFS protocol in Linux and SMB protocol in Windows (NAS scheme). However, the advantage of using iSCSI-based file accesses decreases as the file size increases. The obtained experimental results shed some light on the performance of applications based on iSCSI storage.     

Java multimedia telecollaboration

Using Java-based tools in multimedia collaborative environments accessed over the Internet can increase an application's client base. Most operating systems support Java, and its "compile once-run everywhere" architecture is easy to maintain and update. The Java-based tools presented here let users share Internet resources, including resources originally designed for single use.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.