Robust dual-quantisation multibit sigma-delta modulator

A new dual-quantisation sigma-delta modulator is proposed, which introduces an additional feedback path in the input of the second integrator. In this way, unlike other dual-quantisation architectures, larger signal-to-noise ratios can be obtained by means of aggressive noise-shaping, like in a conventional multibit modulator. The proposed modulator is also shown to be more robust against non-idealities than other dual-quantisation architectures.     

Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation

A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM is proposed in this paper. To this end, the flash quantizer and the digital-to-analog converter (DAC) in a multibit (MB) CT-SDM clocked at a rate f_max are replaced by a single-bit (SB) comparator with hysteresis clocked at a higher rate f_s and a SB-DAC, respectively. By proper selection of the hysteresis in the comparator and the ratio F = f_s/f_max, the performances of both modulators are shown to be equivalent. The comparator with hysteresis and the loop filter produce, in the modulator output, a limit cycle of frequency /max which is modulated by the input signal. Therefore, the modulator output can be considered to be a pulsewidth (PW) modulated signal with a frequency approximately equal to /max, and the proposed modulator is called a PW-SDM. Despite the high sampling rate of the comparator output, the integrators and the SB-DAC of the proposed modulator have the same speed requirements as those of the equivalent conventional MB-SDM. On the other hand, in the proposed modulator there are not MB (analog-to-digital or digital-to-analog) converters. Therefore, for a given set of specifications, the proposed PW-SDM is expected to consume less power and area than its equivalent conventional MB modulator.     

New multirate bandpass sigma-delta modulators

A new architecture for fourth- and sixth-order bandpass sigma-delta (BP-SD) modulators is proposed here. The basic BP-SD modulator is obtained from its low-pass (LP) counterpart by means of the standard transformation z/sup -1/ /spl rarr/ -z/sup -2/, which transforms the integrators in the LP modulator into resonators in the BP modulator, and places the input signal band at the frequency f/sub s//4, where f/sub s/ is the sampling rate. In the proposed architecture, the second resonator (and the third one for the sixth-order case) is implemented using a two-path strategy, by means of two high-pass filters (whose poles are located at f/sub s//2) operating in a time-interleaved mode. However, unlike other BP-SD modulators using the two-path strategy, in our approach, the effective sampling frequency in the second resonator (and in the third one for the sixth-order case) is increased to 2/spl middot/f/sub s/ by maintaining the clock rate of the high-pass filters to f/sub s/ which, in turn, places their poles at f/sub s//2. The signal band in the input of the second resonator is moved from the center frequency f/sub s//4 to f/sub s//2 by a modulation process that separates the signal into their in-phase and quadrature components. Another demodulation process in the digital domain reverses this frequency translation of the signal band before the output signal is converted to the analog domain and fed back to the modulator input. A detailed theoretical analysis of the architecture is done in the paper. Owing to the multirate nature of the proposed modulators, simulation results show an improvement of approximately 12 dB in the input dynamic range (fourth-order case) when compared to conventional modulators of the same order clocked at the same frequency rate (in the first resonator).     

Digital noise-shaping of residues in dual-quantization sigma-delta modulators

A new dual-quantization Sigma-Delta modulator is proposed in this paper where the coarse-quantizer output, obtained from the fine-quantizer output by means of a digital noise-shaping coder, is fed back to the input of the first integrator by means of a p-bit digital-to-analog converter (DAC) (typically, p=1). To avoid the truncation error inserted into the first integrator to propagate to the rest of integrators, the residue of the digital coder is first integrated and then fed to the second integrator through an additional multibit DAC. Unlike other dual-quantization architectures, the proposed one allows to obtain a large signal-to-noise plus distortion ratio by using aggressive noise transfer functions, like in conventional multibit modulators. Mismatch effects on performances are carefully analyzed. It will be shown that more than one digital coder can be included in the architecture in order to reduce the number of bits of the additional DAC. Simulation results are presented which support the theoretical analysis.     

Frequency-to-digital conversion based on a sampled Phase-Locked Loop

A new Frequency-to-Digital (F2D) converter based on a Phase-Locked Loop (PLL) is presented in this paper where the square wave at the output of a Voltage Controlled Oscillator (which is also the PLL output) is sampled and fed back to one of the Phase–Frequency Detector inputs. This sampled output is digitally processed and the information carried in its frequency is converted to a digital signal by means of a digital differentiator. Theoretical analyses and system-level simulations show that the errors produced by the sampling are shaped by a high-order transfer function in the same way as quantization errors are shaped in a Sigma–Delta Modulator. In addition, transistor-level simulations show a low sensitivity to non-linear circuit errors. The proposed F2D converter is suitable for integration in modern nanometer CMOS technologies, and can be used as an FM demodulator.     

Electronic Implementation of Multirate Sigma-Delta Modulators Using CMOS Technologies

Multirating has been recently proposed to reduce the frequency rate of the first integrator(s) of a single-loop, or the first stage(s) of a cascade, Sigma-Delta modulator (SDM). This is a promising technique for the design of high speed, low-power modulators, as the first integrator (or stage) in the chain primarily determines the performances of the modulator, as well as its power consumption. This paper presents the first implementation of a 2nd-order multirate SDM, showing different circuit solutions. The experimental results obtained with a prototype in a standard 0.6 μm CMOS technology shows that different clock rates can be selected for each integrator of a SDM. Alfredo Pérez Vega-Leal was born in Seville, Spain. He received the Telecommunications Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1998 and 2003, respectively. Since 1995, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, as research student and became an Associate Professor in 1999. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion. Francisco Colodro was born in Peal de Becerro (Jaén), Spain, in 1968. He received the Ingeniero de Telecomunicación degree from the University of Vigo, Vigo, Spain, in 1992, and the Ph.D. degree from the University of Sevilla, Sevilla, Spain, in 1997. In 1992 he joined the Department of Electronics Engineering, University of Sevilla, where he is currently and Associate Professor. His research interests are in the architectural study of Σ Δ modulators, the implementation of ADCs based on Σ Δ modulators, and application of electronic circuits and systems to communication. Marta Laguna was born in Seville, Spain. She received the Telecommunications Engineering degree from the University of Seville in 2002. She is currently working toward the Ph.D. degree. Her doctoral work focuses on the design of continuous-time sigma-delta modulators. Since 2001, she has been with the Department of Electronic Engineering, School of Engineering, University of Seville, as research student and became an assistant teacher in 2004. Her research interests are high-speed analog-to-digital converters and sigma-delta modulators. Antonio Torralba (M'89–SM'02) was born in Sevilla, Spain, in 1960. He received the electrical engineering and Ph.D. degrees from the University of Sevilla in 1983, and 1985, respectively. Since 1983 he has been with the Department of Electronics Engineering, School of Engineering, University of Sevilla, where he has been Associate Professor in 1987, and Full Professor since 1996, leading a research group on mixed signal design. In 1999 he made a short stay at the Department of Electrical Engineering, NMSU, and he is presently in the Department of Electrical Engineering, TAMU for a Sabbatical stay. His interests include low-voltage analog circuits and systems, analog to digital conversion, Σ Δ modulators, and electronic circuits and systems with application to control and communication. In these fields he has published around 40 journal papers and more than 100 conference papers, and he holds 2 international patents.     

New class of multibit sigma-delta modulators using multiratearchitecture

A new multibit sigma-delta modulator is presented where the analogue-to-digital converter in the forward path is replaced by an increase in the clock rate of the integrators in the final stages. Theoretical and simulation results are presented for second- and third-order modulators