PowerNap: an efficient power management scheme for mobile devices

We present PowerNap, an OS power management scheme, which can significantly improve the battery life of mobile devices. The key feature of PowerNap is the skipping of the periodic system timer ticks associated with the operating system. On an idle device, this modification increases the time between successive timer interrupts and enables us to put the processor/system into a more efficient low power state. This saves the energy consumed by workless timer interrupts and the excess energy consumed by the processor in less efficient low power states. PowerNap is tightly integrated with the kernel and is designed for optimal control of the latency and energy associated with transitioning in and out of the low power states. We describe an implementation of PowerNap and its impact on system software. Experiments with IBM's WatchPad verify the ability of PowerNap to extend battery life. An analytical model that quantifies the ability of the scheme to reduce power is also presented. The model is in good agreement with experimental results. We apply the model to small form-factor devices which use processors that have a PowerDown state. In such devices, PowerNap may extend battery life by more than 42 percent for small processor workloads and for background power levels below 10 mW.     

Java multimedia telecollaboration

Using Java-based tools in multimedia collaborative environments accessed over the Internet can increase an application's client base. Most operating systems support Java, and its "compile once-run everywhere" architecture is easy to maintain and update. The Java-based tools presented here let users share Internet resources, including resources originally designed for single use.     

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-/spl mu/m CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.     

Lateral ion implant straggle and mask proximity effect

Lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices. The threshold voltage of both NMOSFETs and PMOSFETs increases in magnitude for conventional retrograde wells, but for triple-well isolated NMOSFETs the threshold voltage decreases for narrow devices near the edge of the well. Electrical data, SIMS, and SUPREM4 simulations are shown that elucidate the phenomenon.     

Asymptotic performance of single parity-check product codes

This article investigates the asymptotic performance of single parity-check (SPC) product codes (PCs) from a decoding point of view. Specifically, the probability of bit error is bounded before and after the decoding of each dimension, similar to the analysis of "iterated codes" by Elias (1954). It is shown that the asymptotic probability of bit error can be driven to zero as the number of dimensions, and hence the block length, increases at signal-to-noise ratios (SNRs) within 2 dB of capacity over the additive white Gaussian noise (AWGN) channel.     

Switched-Current Filters Revisited: Square-Root Domain Sampled-Data Filters

In this brief, the well-known switched-current (SI) filtering technique is revisited using the concept of the square-root domain (SRD) filtering. It is proved that SI filters are a subclass of the SRD filters, where sampled-data signal processing is performed. This is achieved by considering typical lossless and lossy SRD sampled-data integrator configurations, using a set of complementary SRD operators which are based on the quadratic I-V relationship of MOS transistor operated in the saturation. Circuit examples are given, where linear-domain integrator and third-order filter configurations were derived using appropriate SRD sampled-data building blocks     

Profile-Driven Component Placement for Cluster-Based Online Services

The growth of the Internet and of various intranets has spawned a wealth of online services, most of which are implemented on local-area clusters using remote invocation (for example, remote procedure call/remote method invocation) among manually placed application components. Component placement can be a significant challenge for large-scale services, particularly when application resource needs are workload dependent. Automatic component placement has the potential to maximize overall system throughput. The key idea is to construct (offline) a mapping between input workload and individual-component resource consumption. Such mappings, called component profiles, then support high-performance placement. Preliminary results on an online auction benchmark based on J2EE (Java 2 Platform, Enterprise Edition) suggest that profile-driven tools can identify placements that achieve near-optimal overall throughput.