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含集中质量悬臂输流管的稳定性与模态演化特性研究 总被引:2,自引:0,他引:2
本文主要研究通过调控集中质量对悬臂输流管稳定性和振动模态特性的影响规律,为输流管动力学性能的可控性提供理论指导和实验依据. 首先基于扩展的哈密顿原理,建立了含集中质量悬臂输流管的非线性动力学理论模型. 基于线性动力学特性分析,研究发现集中质量沿管道轴向位置变化对输流管发生颤振失稳的临界流速有重要影响.并通过伽辽金前四阶模态截断处理线性矩阵方程式,定性地分析了集中质量位置与质量比的变化对于输流管稳定性影响的变化.实验结果表明, 输流管的颤振失稳模态随集中质量位置的变化发生了转迁. 此外,基于动力学理论分析, 发现集中质量比值对失稳临界流速也有重要的影响,且主要取决于集中质量的安装位置. 基于非线性特性,进一步分析了集中质量对输流管振动幅值的影响. 实验和理论研究发现,集中质量位置从固定端向自由端变化时, 输流管振幅表现出先增大后减小趋势,且振动模态也从二阶转迁到三阶.本研究有望为输流管振动驱动应用提供理论支撑与指导意义. 相似文献
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A low specific on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) metal-oxide semiconductor field-effect transistor(MOSFET) is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer(BOX)(DGRD MOSFET).First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage(BV).The BV of 233 V and Ron,sp of 4.151 mΩ·cm2(VGS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes. 相似文献
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A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS 下载免费PDF全文
A novel low specific on-resistance(R on,sp) silicon-on-insulator(SOI) p-channel lateral double-diffused metal-oxide semiconductor(pLDMOS) compatible with high voltage(HV) n-channel LDMOS(nLDMOS) is proposed.The pLDMOS is built in the N-type SOI layer with a buried P-type layer acting as a current conduction path in the on-state(BP SOI pLDMOS).Its superior compatibility with the HV nLDMOS and low voltage(LV) complementary metal-oxide semiconductor(CMOS) circuitry which are formed on the N-SOI layer can be obtained.In the off-state the P-buried layer built in the NSOI layer causes multiple depletion and electric field reshaping,leading to an enhanced(reduced) surface field(RESURF) effect.The proposed BP SOI pLDMOS achieves not only an improved breakdown voltage(BV) but also a significantly reduced Ron,sp.The BV of the BP SOI pLDMOS increases to 319 V from 215 V of the conventional SOI pLDMOS at the same half cell pitch of 25 μm,and R on,sp decreases from 157 mΩ·cm2 to 55 mΩ·cm2.Compared with the PW SOI pLDMOS,the BP SOI pLDMOS also reduces the R on,sp by 34% with almost the same BV. 相似文献
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本文介绍基于VDMOS结构的浮栅MOS管存储机理核辐射探测器的基本概念,简要介绍了浮栅MOS管的结构设计、制作和测试。 相似文献
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为研究打磨参数对钢轨打磨磨石磨损的影响,利用SOLIDWORKS三维软件建立了钢轨打磨模型,在DEFORM-3D有限元软件中设置相应的仿真参数,仿真分析了打磨转速、进给速度及打磨深度对打磨磨石磨损的影响,研究了钢轨材料去除量随打磨参数的变化情况.结果表明:打磨磨石磨损量随打磨距离近似呈线性增长趋势;打磨磨石磨损量随打磨转速和打磨深度的增加而增加,随进给速度的增加而减小;钢轨材料打磨去除量变化趋势同打磨磨石的磨损量相一致,而且二者的变化原因也是相辅相成的.研究结果为现场钢轨打磨参数优化提供了重要的理论依据. 相似文献
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Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer 下载免费PDF全文
A new ultra-low specific on-resistance(Ron,sp) vertical double diffusion metal–oxide–semiconductor field-effect transistor(VDMOS) with continuous electron accumulation(CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration(Nn). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp.Especially, the two PN junctions within the trench gate support a high gate–drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS(CSJ-VDMOS)at the same high breakdown voltage(BV). 相似文献