A continuous analytic channel potential solution to doped symmetric double-gate MOSFETs from the accumulation to the strong-inversion region

A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate (DG) MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.     

Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs

This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and drain-induced barrier-lowering of CMOS-based devices in nanometre scale.     

Extraordinarily high drive currents in asymmetrical double-gate MOSFETs

Numerical simulation results derived from a Schrödinger–Poisson tool applied to scaled double-gate (DG) MOSFETs, supplemented by analytical characterizations of the pertinent physics, are presented to give insight concerning the near-ideal features of DG devices and to explain how the low-voltage drive current of the asymmetrical DG MOSFET, having only one predominant channel, can be comparable to, and even higher than, that of the symmetrical-gate counterpart designed to have the same off-state current.     

Erratum to "Quantum compact model for thin-body double-gate Schottky barrier MOSFETs"

<正>The statement for the third paragraph of the right column of page 3079 (Chinese Physics B, 2008, Vol. 17,No. 8, pp. 3077-3082 )[1]is inappropriate. This paragraph should be restated as follows.     

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.     

Quantum compact model for thin-body double-gate Schottky barrier MOSFETs

Nanoscale Schottky barrier metal oxide semiconductor field-effect transistors （MOSFETs） are explored by using quantum mechanism effects for thin-body devices. The results suggest that for small nonnegative Schottky barrier heights, even for zero barrier height, the tunnelling current also plays a role in the total on-state current. Owing to the thin body of device, quantum confinement raises the electron energy levels in the silicon, and the tradeoff takes place between the quantum confinement energy and Schottky barrier lowering （SBL）. It is concluded that the inclusion of the quantum mechanism effect in this model, which considers an infinite rectangular well with a first-order perturbation in the channel, can lead to the good agreement with numerical result for thin silicon film. The error increases with silicon thickness increasing.     

Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (I_on), off-current (I_off), subthreshold swing (S), and I_on/I_off ratio. In addition, the dependences of intrinsic delay time (τ) and radio-frequency (RF) performances including cut-off frequency (f_T) and maximum oscillation frequency (f_max) on gate–drain capacitance (C_gd) with the underlapping were investigated as the gate length (L_gate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions.     

对称三材料双栅应变硅金属氧化物半导体场效应晶体管二维解析模型

提出了对称三材料双栅应变硅金属氧化物半导体场效应晶体管器件结构,为该器件结构建立了全耗尽条件下的表面势模型、表面场强和阈值电压解析模型,并分析了应变对表面势、表面场强和阈值电压的影响,讨论了三栅长度比率对阈值电压和漏致势垒降低效应的影响,对该结构器件与单材料双栅结构器件的性能进行了对比研究.结果表明,该结构能进一步提高载流子的输运速率,更好地抑制漏致势垒降低效应.适当优化三材料栅的栅长比率,可以增强器件对短沟道效应和漏致势垒降低效应的抑制能力.     

A deterministic method study of the impact of the Pauli principle in double-gate MOSFETs

The Pauli principle is included in a multisubband deterministic solver for two-dimensional devices without approximations.The nonlinear Boltzmann equations are treated properly without compromising on accuracy,convergence,or CPU time.The simulation results indicate the significant impact of the Pauli principle on the transport properties of the quasi-2D electron gas,especially for the on state.     

Simulation of CMOS logic inverter based on vertically stacked polycrystalline silicon nanosheet gate-all-around MOSFET and its electrical characteristics

The DC and inverter characteristics for the position of a single grain boundary (GB) in a nanosheet gate-all-around (GAA) MOSFET based on poly-crystalline silicon with three channels were analyzed. For the same channel layer, owing to the band banding by the drain voltage, the GB displays decreasing influence on the current as it moves towards the drain. The GB exhibits the highest on-state current of 6.89 × 10⁻⁴ A/μm when it is located at the drain. The DC characteristics determine the noise margin and delay time of the inverter. The higher the induced current, the lower the noise margin and delay time of the NMOS leading to improved characteristics of the inverter. The delay time when the GB existed in the drain, was considered to be the best in terms of DC performance as it was the lowest at 6.47 ps and showed 8.3% improvement in the switching characteristics.     

Corner exponents in the two-dimensional Potts model

The critical behavior at a corner in two-dimensional Ising and three-state Potts models is studied numerically on the square lattice using transfer operator techniques. The local critical exponents for the magnetization and the energy density for various opening angles are deduced from finite-size scaling results at the critical point for isotropic or anisotropic couplings. The scaling dimensions compare quite well with the values expected from conformal invariance, provided the opening angle is replaced by an effective one in anisotropic systems.     

一种改进的SUSAN角点提取方法

针对基本SUSAN算法存在漏检测、处理速度慢以及容易产生伪角点等问题,提出了一种改进的SUSAN角点提取算法。首先对图像的像素点按边缘点、内部点和背景点进行分类,在此基础上只对边缘点进行SUSAN算法处理,然后检查已经提取到的所有角点,剔除同一区域范围内的伪角点,从而实现对大部分角点的快速、准确提取。实验结果表明,该算法的运算速度比改进前提高约一倍,能够较准确地检测到目标角点。     

Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III–V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (t_epi) and height of source region (H_source) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (I_on) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (V_t) of 0.1 V, current gain cut-off frequency (f_T) of 12 GHz, and maximum oscillation frequency (f_max) of 283 GHz.     

特定边界跟踪中角点检测研究

针对边界跟踪算法中在角点附近丢失边界信息的问题,对待检测边界中角点的判别和检测方法进行了研究。分析了边界搜索中所扩展的邻域的半径和角点位置的关系,提出了角点存在判据,给出了角点存在区间。提出了寻区间法角点检测算法,用5个已知边界点之间的关系,判断出角点存在的邻域,通过选取合适的邻域半径,使角点存在区间向角点收敛。对测试图像和人侧面轮廓图像的边界利用所提出的算法进行跟踪,测试图像的边界点从19个增长为37个,人侧面轮廓图像边界点从13个增长为21个,新算法准确地检测到轮廓角点和后续种子点,使边界跟踪能够反映所有的边界信息。     

Corner spontaneous magnetization

Details are given of a new method allowing an exact calculation of the spontaneous magnetization in the corner as well as along the edge at an arbitrary distance of the corner for a rectangular planar Ising ferromagnet.     

Effective Reflection Area of a Cube Corner Retroreflector

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Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs

An analytical model for subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs is presented in this paper. Both the drift and diffusion components of current densities are considered for the modeling of subthreshold current. Virtual cathode concept of DG MOSFETs is utilized to model the subthreshold swing of TM-DG MOSFETs. The effect of different length ratios of the three channel regions under three different gate materials of device on the subthreshold current and subthreshold swing of the short-channel TM-DG MOSFETs have been discussed. The dependencies of subthreshold current and subthreshold swing on various device parameters have been studied. The simulation data obtained by using the commercially available 2D device simulation software ATLAS™ has been used to validate the present model.     

角锥棱镜腔Nd:YAG/Cr4+:YAG被动锁模激光器的研究

理论分析并数值模拟了腔内光强随角锥棱镜旋转的变化,实验证明在角锥棱镜腔Nd:YAG/Cr4 :YAG被动锁模激光器中,偏振耦合输出得到了锁模深度和锁模几率近乎100%的线偏振被动锁模脉冲输出.通过旋转角锥棱镜改变偏振耦合输出、调节腔内光强,可以得到被动锁模和被动调Q两种状态的脉冲输出,脉冲能量166.5 mJ/pulse,脉冲动静比高达59.7%.     

Corner transfer matrices of the triangular Ising model

Recently, a new technique for investigating the zero-field, eight-vertex model on the square lattice using corner transfer matrices was suggested by Baxter. In this paper these ideas are applied to the anisotropic, ferromagnetic, triangular Ising lattice in zero field below its critical temperature. The diagonal form of the corner transfer matrix for the triangular lattice shows essentially the same structure as that for the square Ising lattice. The spontaneous magnetization can be obtained easily and agrees with that previously derived.     

针对标定图像中Harris伪角点的自动修正算法

针对Harris算子在提取标定图像中的特征点时可能出现的伪角点,提出了一种新的自动修正算法.通过对伪角点邻域内图像进行X和Y两个方向上的一维亚像素扫描,然后用基于正交距离的直线或曲线拟合算法计算两条边缘线条,最后用两边缘线条的交点来估计正确角点位置.本文对机器视觉标定中的棋盘格图像进行大量实验,结果证明该方法具有较好的鲁棒性,达到了预期的两个目的:1)修正图像中的伪角点;2)得到高准确度的亚像素角点.