Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism

For the first time, we have presented a novel nanoscale fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI-MOSFET) with modified current mechanism for leakage current reduction. The key idea in this work is to suppress the leakage current by injected carriers decrement into the channel from the source in weak inversion regime while we have created a built-in electric field in the channel for improving the on current of device. Therefore, we have introduced a trapezoidal doping that distributed vertically in the channel and called the proposed structure as vertical trapezoid doping fully depleted silicon-on-insulator MOSFET (VTD-SOI). Using two-dimensional two-carrier simulation we demonstrate that the VTD-SOI decreases the leakage current in comparison with conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI). Also, our results show short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement in the proposed structure. Therefore, the VTD-SOI structure shows excellent performance for scaled transistors in comparison with the C-SOI and can be a good candidate for CMOS low power circuits.     

Three-dimensional vertical ZnO transistors with suspended top electrodes fabricated by focused ion beam technology

Three-dimensional(3D)vertical architecture transistors represent an important technological pursuit,which have distinct advantages in device integration density,operation speed,and power consumption.However,the fabrication processes of such 3D devices are complex,especially in the interconnection of electrodes.In this paper,we present a novel method which combines suspended electrodes and focused ion beam(FIB)technology to greatly simplify the electrodes interconnection in 3D devices.Based on this method,we fabricate 3D vertical core-double shell structure transistors with ZnO channel and Al₂O₃ gate-oxide both grown by atomic layer deposition.Suspended top electrodes of vertical architecture could be directly connected to planar electrodes by FIB deposited Pt nanowires,which avoid cumbersome steps in the traditional 3D structure fabrication technology.Both single pillar and arrays devices show well behaved transfer characteristics with an Ion/Ioff current ratio greater than 106 and a low threshold voltage around 0 V.The ON-current of the 2×2 pillars vertical channel transistor was 1.2μA at the gate voltage of 3 V and drain voltage of 2 V,which can be also improved by increasing the number of pillars.Our method for fabricating vertical architecture transistors can be promising for device applications with high integration density and low power consumption.     

A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure

Diode currents of MOSFET were studied and characterized in detail for the ion implanted pn junction of short channel MOSFETs with shallow drain junction doping structure. The diode current in MOSFET junctions was analyzed on the point of view of the gate-induced-drain leakage (GIDL) current. We could found the GIDL current is generated by the band-to-band tunneling (BTBT) of electrons through the reverse biased channel-to-drain junction and had good agreement with BTBT equation. The effect of the lateral electric field on the GIDL current according to the body bias voltage is characterized and discussed. We measured the electrical doping profiling of MOSFETs with a short gate length, ultra thin oxide thickness and asymmetric doped drain structure and checked the profile had good agreement with simulation result. An accurate effective mobility of an asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique.     

Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

In this paper, we present a novel nano-scale fully depleted silicon-on-insulator metal-oxide semiconductor field-effect transistor (SOI MOSFET). On-state current increment, leakage current decrement, and self-heating effect improvement are pursued in our proposed structure. The structure makes use of a buried insulator layer which consists of two materials to reduce the self-heating effect. On the other hand, to modify the sub- and super-threshold drain current, vertical trapezoidal doping distribution and additional side gate technique are employed. Our novel transistor is named dual material buried insulator vertical trapezoidal doping SOI MOSFET (DV-SOI MOSFET). We investigate the electrical performance and thermal behavior of the DV-SOI MOSFET using a commercial device simulator. We demonstrate that the proposed structure increases on–off current ratio by orders of magnitude and considerably improves self-heating effect in comparison with the conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI) which uses side gate for better electrical performance.     

LDC-CNTFET: A carbon nanotube field effect transistor with linear doping profile channel

In this paper, a novel carbon nanotube field effect transistor with linear doping profile channel (LDC-CNTFET) is presented. The channel impurity concentration of the proposed structure is at maximum level at source side and linearly decreases toward zero at drain side. The simulation results show that the leakage current, on-off current ratio, subthreshold swing, drain induced barrier lowering, and voltage gain of the proposed structure improve in comparison with conventional CNTFET. Also, due to spreading the impurity throughout the channel region, the proposed structure has superior performance compared with a single halo CNTFET structure with equal saturation current. Design considerations show that the proposed structure enhances the device performance all over a wide range of channel lengths.     

对称三材料双栅应变硅金属氧化物半导体场效应晶体管二维解析模型

提出了对称三材料双栅应变硅金属氧化物半导体场效应晶体管器件结构,为该器件结构建立了全耗尽条件下的表面势模型、表面场强和阈值电压解析模型,并分析了应变对表面势、表面场强和阈值电压的影响,讨论了三栅长度比率对阈值电压和漏致势垒降低效应的影响,对该结构器件与单材料双栅结构器件的性能进行了对比研究.结果表明,该结构能进一步提高载流子的输运速率,更好地抑制漏致势垒降低效应.适当优化三材料栅的栅长比率,可以增强器件对短沟道效应和漏致势垒降低效应的抑制能力.     

Novel carbon nanotube field effect transistor with graded double halo channel

A novel carbon nanotube field effect transistor with symmetric graded double halo channel (GDH–CNTFET) is presented for suppressing band to band tunneling and improving the device performance. GDH structure includes two symmetric graded haloes which are broadened throughout the channel. The doping concentration of GDH channel is at maximum level at drain/source side and is reduced gradually toward zero at the middle of channel. The doping distribution at source side of channel reduces the drain induced barrier lowering (DIBL) and the drain side suppresses the band to band tunneling effect. In addition, broadening the doping throughout the channel increases the recombination of electrons and holes and acts as an additional factor for improving the band to band tunneling. Simulation results show that applying this structure on CNTFET enhances the device performance. In comparison with double halo structure with equal saturation current, the proposed GDH structure shows better characteristics and short channel parameters. Furthermore, the delay and power delay product (PDP) analysis versus on/off current ratio shows the efficiency of the proposed GDH structure.     

Self-aligned metal-SiO2-InP based MISFETS having modulation doped channels

A novel metal-SiO₂-InP MISFET (metal-insulator-semiconductor field effect transistor) structure is proposed. This device incorporates a modulation doped channel and the self-aligned gate feature of Si MOSFETs. The modulation doping provides very high electron mobility and the self-alignment of gate, source and drain provides high packing density. Analytical results on current-voltage and transconductance characteristics are presented. Significant enhancement in high frequency performance over conventional MISFETs, employing SiO₂ as an insulator, is reported.     

Performance Analyses of Planar Schottky Barrier MOSFETs with Dual Silicide Layers at Source/Drain on Bulk Substrates and Material Studies of ErSi_x/CoSi_2/Si Stack Interface

A dual silicide layer structure is proposed for Schottky barrier metal-oxide-semiconductor held effect transistors(MOSFETs) on bulk substrates.The source/drain regions are designed to be composed with dual stacked silicide layers,forming different barrier heights to silicon channel.Performance comparisons between the dual barrier structure and the single barrier structure are carried out with numerical simulations.It is found that the dual barrier structure has significant advantages over the single barrier structure because the drive current and leakage current of the dual barrier structure can be modulated.Furthermore,the dual barrier structure's performance is nearly insensitive to the total silicide thickness,which can relax the fabrication requirements and even make an SOI substrate unnecessary for planar device design.The formation of ErSi_x/CoSi_2 stacked multilayers has been proved by experiments.     

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software.     

绝缘体上硅金属氧化物半导体场效应晶体管中辐射导致的寄生效应研究

基于⁶⁰Co γ射线源研究了总剂量辐射对绝缘体上硅（silicon on insulator,SOI）金属氧化物半导体场效应晶体管器件的影响.通过对比不同尺寸器件的辐射响应,分析了导致辐照后器件性能退化的不同机制.实验表明：器件的性能退化来源于辐射增强的寄生效应;浅沟槽隔离（shallow trench isolation,STI）寄生晶体管的开启导致了关态漏电流随总剂量呈指数增加,直到达到饱和;STI氧化层的陷阱电荷共享导致了窄沟道器件的阈值电压漂移,而短沟道器件的阈值电压漂移则来自于背栅阈值耦合;在同一工艺下,尺寸较小的器件对总剂量效应更敏感.探讨了背栅和体区加负偏压对总剂量效应的影响,SOI器件背栅或体区的负偏压可以在一定程度上抑制辐射增强的寄生效应,从而改善辐照后器件的电学特性.     

Nanoscale SiGe-on-insulator (SGOI) MOSFET with graded doping channel for improving leakage current and hot-carrier degradation

A novel graded doping profile, for the first time is introduced for reliability improvement and leakage current reduction. The proposed structure is called graded doping channel SiGe-on-insulator (GDC-SGOI). The key idea in this work is to modify the electric field and band energy with novel doping distribution in the channel for improving leakage current and hot electron. Using two-dimensional two-carrier simulation we demonstrate that the GDC-SGOI shows lower electron temperature near the drain region in the channel in comparison with the conventional SGOI (C-SGOI) with uniform doping. On the other hand, short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement leads to leakage current reduction. DIBL decrement and less dependence of the threshold voltage and DIBL on channel length variation in the GDC-SGOI structure show SCEs suppression. Furthermore the on-off current ratio (I_on/I_off) in the GDC-SGOI is higher than that achieved from the C-SGOI. Therefore, the results show that the GDC-SGOI structure especially in low power and device reliability has excellent performance in comparison with the C-SGOI.     

Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs

An analytical model for subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs is presented in this paper. Both the drift and diffusion components of current densities are considered for the modeling of subthreshold current. Virtual cathode concept of DG MOSFETs is utilized to model the subthreshold swing of TM-DG MOSFETs. The effect of different length ratios of the three channel regions under three different gate materials of device on the subthreshold current and subthreshold swing of the short-channel TM-DG MOSFETs have been discussed. The dependencies of subthreshold current and subthreshold swing on various device parameters have been studied. The simulation data obtained by using the commercially available 2D device simulation software ATLAS™ has been used to validate the present model.     

The effects of source/drain and gate overlap on the performance of carbon nanotube field effect transistors

At nanometer regime, fabricating the structures with non-overlapped channel and abrupt doping profile is very complicated and sometimes impossible. So, the resultant device experiences some non-ideal effects which have to be predicted and well addressed by simulation before fabrication. In this paper the effects of overlap between gate and source/drain regions on the performance of carbon nanotube field effect transistors have been investigated. The overlapped structure has been simulated with various doping profiles at drain/source and gate region junction tip. The device performance has been investigated in terms of ON current, Off current, ON/Off current ratio, subthreshold swing, delay, and power delay product (PDP). Simulations show that depending on the variations in the effective channel length, the overlap deteriorates some device characteristics and enhances the others. Where the effective channel length decreases (increases), the overlap deteriorates (enhances) the current ratio and subthreshold swing but enhances (deteriorates) the delay and PDP compared to non-overlapped structure. Furthermore, the overlapped structure with graded profile results in lower current ratio and higher subthreshold swing compared to overlapped structure with abrupt profile. At a fixed current ratio, the delay and PDP of overlapped structure with graded profile are more than overlapped structure with abrupt profile but at a fixed channel length, both profiles have approximately equal delay and PDP.     

Turning the world vertical: MOSFETs with current flow perpendicular to the wafer surface

Tremendous progress in information technology has been made possible by the development and optimization of metal oxide semiconductor field effect transistor (MOSFET) devices. For the last three decades, the dimensions of the devices have been scaled down and the complexity of the integrated circuits increased according to Moore’s law. Further scaling of the devices has been predicted by the international technology roadmap for semiconductors (ITRS). To meet the future technological requirements, much effort has been expended on increasing the capabilities of MOSFETs. Both new materials and new designs have been introduced to maintain device scaling. Most new designs were improvements of the normal planar design of the device, such as SOI and ultrathin body devices. In so-called FinFET structures, current flows through a thin silicon fin and is controlled by two gates in parallel on both sides of the fin. Vertical MOSFET devices represent a new category. In these structures the planar arrangement of the source gate and drain is turned through 90° so that they are positioned on top of each other and the current flow is perpendicular to the surface. By utilizing the 3rd dimension, the channel length can be adjusted by layer deposition and thus dispensing with advanced (and expensive) lithography. Furthermore, depending on the application, the vertical designs require less space than planar ones so that it is possible to increase integration density. The present paper gives a review of vertical MOSFET devices with current flow perpendicular to the surface. PACS 85.30     

A spin field effect transistor for low leakage current

In a spin field effect transistor, a magnetic field is inevitably present in the channel because of the ferromagnetic source and drain contacts. This field causes random unwanted spin precession when carriers interact with non-magnetic impurities. The randomized spins lead to a large leakage current when the transistor is in the “off”-state, resulting in significant standby power dissipation. We can counter this effect of the magnetic field by engineering the Dresselhaus spin–orbit interaction in the channel with a backgate. For realistic device parameters, a nearly perfect cancellation is possible, which should result in a low leakage current.     

GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

GaSb p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)with an atomic layer deposited Al2O3gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated.Temperature dependent electrical characteristics are investigated.Different electrical behaviors are observed in two temperature regions,and the underlying mechanisms are discussed.It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current,which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions.Methods to further reduce the off-state drain leakage current are given.     

Model and analysis of drain induced barrier lowering effect for 4H--SiC metal semiconductor field effect transistor

Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL (drain induced barrier lowering) effect for short channel 4H--SiC metal semiconductor field effect transistors (MESFETs). An accurate analytical model of threshold voltage shift for the asymmetric short channel 4H--SiC MESFET is presented and thus verified. According to the presented model, it analyses the threshold voltage for short channel device on the L/a (channel length/channel depth) ratio, drain applied voltage V_DS and channel doping concentration N_D, thus providing a good basis for the design and modelling of short channel 4H--SiC MESFETs device.     

3D quantum mechanical simulation of square nanowire MOSFETs by using NEGF method

In order to investigate the specifications of nanoscale transistors, we have used a three dimensional (3D) quantum mechanical approach to simulate square cross section silicon nanowire (SNW) MOSFETs. A three dimensional simulation of silicon nanowire MOSFET based on self consistent solution of Poisson-Schrödinger equations is implemented. The quantum mechanical transport model of this work uses the non-equilibrium Green’s function (NEGF) formalism. First, we simulate a double-gate (DG) silicon nanowire MOSFET and compare the results with those obtained from nanoMOS simulation. We understand that when the transverse dimension of a DG nanowire is reduced to a few nanometers, quantum confinement in that direction becomes important and 3D Schrödinger equation must be solved. Second, we simulate gate-all-around (GAA) silicon nanowire MOSFETs with different shapes of gate. We have investigated GAA-SNW-MOSFET with an octagonal gate around the wire and found out it is more suitable than a conventional GAA MOSFET for its more I _on /I _off , less Drain-Induced-Barrier-Lowering (DIBL) and less subthreshold slope.     

Suppression of the tunneling effect by shallow junctions in field-effect transistor

We study the quantum wave transport in nanoscale field-effect transistors. It has been shown that the tunneling effect between the source and the drain in an ultra-short channel transistor significantly degrades the control of the drain current by the gate. However, the tunneling effect is suppressed by reducing the depth of the source and drain junctions which is designated to suppress the short-channel effects concerning the cut-off characteristics of the field-effect transistor. The reduced junction depth confines the carriers in the direction (y -direction) perpendicular to the transport direction (x -direction). The matching of y -direction wavefunctions at regional boundaries suppresses the tunneling effect and normal FET current–voltage characteristics has been obtained, which explains theoretically the successful fabrication of nanoscale field-effect transistors.