Comparison of hot-hole injections in ultrashort channel LDD nMOSFETs with ultrathin oxide under an alternating stress

The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain (LDD) nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injections, i.e. low gate voltage hot hole injection (LGVHHI), gate-induced drain leakage induced hot-hole injection (GIDLIHHI) and substrate hot-hole injection (SHHI), have different influences on the devices damaged already by the previous hot electron injection (HEI) because of the different locations of trapping holes and interface states induced by the three types of injections, i.e. three types of stresses. Experimental results show that GIDLIHHI and LGVHHI cannot recover the degradation of electron trapping, but SHHI can. Although SHHI can recover the device's performance, the recovery is slight and reaches saturation quickly, which is suggested here to be attributed to the fact that trapped holes are too few and the equilibrium is reached between the trapping and releasing of holes which can be set up quickly in the ultrathin oxide.     

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and V_h degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.     

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

电压应力下超薄栅氧化层n-MOSFET的击穿特性

研究了90nm工艺下栅氧化层厚度为1.4nm的n-MOSFET的击穿特性，包括V-ramp(斜坡电压)应力下器件栅电流模型和CVS(恒定电压应力)下的TDDB(经时击穿)特性，分析了电压应力下器件的失效和退化机理.发现器件的栅电流不是由单一的隧穿引起，同时还有电子的翻越和渗透.在电压应力下，SiO₂中形成的缺陷不仅降低了SiO₂的势垒高度，而且等效减小了SiO₂的厚度(势垒宽度).另外，每一个缺陷都会形成一个导电通道，这些导电通道的形成增大了栅电流，导致器件性能的退化，同时栅击穿时间变长. 关键词： 超薄栅氧化层 斜坡电压 经时击穿 渗透     

Low voltage substrate current： a monitor for interface states generation in ultra-thin oxide n-MOSFETs under constant voltage stresses

The low voltage substrate current （Ib） has been studied based on generation kinetics and used as a monitor of interface states （Nit） generation for ultra-thin oxide n-MOSFETs under constant voltage stress. It is found that the low voltage Ib is formed by electrons tunnelling through interface states, and the variations of Ib（△Ib） are proportional to variations of Nit （△Nit）. The Nit energy distributions were determined by differentiating Nit（Vg）. The results have been compared with that measured by using gate diode technique.[第一段]     

Snapback应力引起的90 nm NMOSFET's栅氧化层损伤研究

实验结果发现突发击穿(snapback)，偏置下雪崩热空穴注入NMOSFET栅氧化层，产生界面态，同时空穴会陷落在氧化层中.由于栅氧化层很薄，陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱，使得栅隧穿电流不断增大.这些氧化层电子陷阱俘获电子后带负电，引起阈值电压增大、亚阈值电流减小.关态漏泄漏电流的退化分两个阶段：第一阶段亚阈值电流是主要成分，第二阶段栅电流是主要成分.在预加热电子(HE)应力后，HE产生的界面陷阱在snapback应力期间可以屏蔽雪崩热空穴注入栅氧化层，使器件snapback开态和关态特性退化变小. 关键词： 突发击穿 软击穿 应力引起的泄漏电流 热电子应力     

多晶SiGe栅量子阱pMOSFET阈值电压模型

本文基于多晶SiGe栅量子阱SiGe pMOSFET器件物理,考虑沟道反型时自由载流子对器件纵向电势的影响,通过求解泊松方程,建立了p+多晶SiGe栅量子阱沟道pMOS阈值电压和表面寄生沟道开启电压模型.应用MATLAB对该器件模型进行了数值分析,讨论了多晶Si_1-yGe_y栅Ge组分、Si_1-xGe_x量子阱沟道Ge组分、栅氧化层厚度、Si帽层厚度、沟道区掺杂浓度和 关键词： 多晶SiGe栅 寄生沟道 量子阱沟道 阈值电压     

具有poly-Si$lt;sub$gt;1-$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;Ge$lt;sub$gt;$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;栅的应变SiGep型金属氧化物半导体场效应晶体管阈值电压漂移模型研究

针对具有poly-Si_1-xGe_x栅的应变SiGe p型金属氧化物半导体场效应晶体管(PMOSFET), 研究了其垂直电势与电场分布, 建立了考虑栅耗尽的poly-Si_1-xGe_x栅情况下该器件的等效栅氧化层厚度模型, 并利用该模型分析了poly-Si_1-xGe_x栅及应变SiGe层中Ge组分对等效氧化层厚度的影响. 研究了应变SiGe PMOSFET热载流子产生的机理及其对器件性能的影响, 以及引起应变SiGe PMOSFET阈值电压漂移的机理, 并建立了该器件阈值电压漂移模型, 揭示了器件阈值电压漂移随电应力施加时间、栅极电压、poly-Si_1-xGe_x栅及应变SiGe层中Ge组分的变化关系. 并在此基础上进行了实验验证, 在电应力施加10000 s时, 阈值电压漂移0.032 V, 与模拟结果基本一致, 为应变SiGe PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础. 关键词： 应变SiGep型金属氧化物半导体场效应晶体管 1-xGe_x栅')" href="#">poly-Si_1-xGe_x栅 热载流子 阈值电压     

低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

开态应力下电压和电流对AlGaN/GaN高电子迁移率晶体管的退化作用研究

通过采集等功率的两种不同开态直流应力作用下AlGaN/GaN高电子迁移率晶体管(HEMTs)漏源电流输出特性、源区和漏区大信号寄生电阻、转移特性、阈值电压随应力时间的变化, 并使用光发射显微镜观察器件漏电流情况, 研究了开态应力下电压和电流对AlGaN/GaN高电子迁移率晶体管的退化作用. 结果表明, 低电压大电流应力下器件退化很少, 高电压大电流下器件退化较明显. 高电压是HEMTs退化的主要因素, 栅漏之间高电场引起的逆压电效应对参数的永久性退化起决定性作用. 除此之外, 器件表面损坏部位的显微图像表明低电压大电流下器件失效是由于局部电流密度过高, 出现热斑导致器件损伤引起的.     

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack(TMGS) DG-MOSFET

In the present work, a two-dimensional(2D) analytical framework of triple material symmetrical gate stack(TMGS)DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS~(TM) device simulator to affirm and formalize the proposed device structure.