Low-temperature fabrication of p+-n diodes with300-Å junction depth

Gas immersion laser doping (GILD) was used to fabricate p⁺ -n diodes with 300-Å junction depth. These diodes exhibit ideality factors of 1.01-1.05 over seven decades of current, reverse leakage current densities ⩽10 nA/cm² at -5-V reverse bias, breakdown voltages above 100 V, and electrical activation of the boron impurity to concentrations approaching 1×10²¹ atoms/cm³. This behavior is achieved without the use of a furnace or rapid thermal anneal     

Formation of shallow p+-n junctions using boron-nitride solid diffusion source

Shallow p⁺-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm², indicating the possibility of this method to form PMOS source-drain contacts.     

Enhancement of oxide break-up by implantation of fluorine inpoly-Si emitter contacted p+-n shallow junctionformation

In this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p⁺-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900°C. As a result, the junction depth of the BF₂-implanted device is much larger than that of the boron-implanted device     

Fully implanted InP JFET with an abrupt p+-n junction

We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p⁺-n junction. The device was made on a semi-insulating InP substrate with Si⁺⁺implant for the n-channel and Be/P co-implant for the p⁺-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 10¹⁶/cm³.     

Characterization of ultra-shallow p+-n junction diodesfabricated by 500-eV boron-ion implantation

Ultrashallow gated diodes have been fabricated using 500-eV boron-ion implantation into both Ge-preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at either 950°C or 1050°C were determined to be 60 and 80 nm, respectively. These are reportedly the shallowest junctions formed via ion implantation. Consideration of several parameters, e.g. reduced B⁺ channeling, increased activation, and reduced junction leakage current, lead to the selection of 15 keV as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850°C/10-s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/cm² for the 60-nm junctions and diode ideality factors for crystalline and preamorphized substrates ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850°C, the leakage current was only 11 nA/cm ². The final junction depths were found to be approximately the same for both preamorphized and nonpreamorphized samples after annealing at 950°C and 1050°C. However, the preamorphized sample exhibited significantly improved dopant activation     

Very-shallow low-resistivity p+-n junctions for CMOS technology

Shallow p-n junctions 110 nm deep have been fabricated using rapid thermal diffusion from a spin-on oxide source. Surface concentrations greater than 3 × 10²⁰cm^-3are possible, with sheet resistivities less than 100 Ω/sq and a maximum reverse-bias leakage at 5 V of 3 nA.cm^-2. Results from 150-nm junctions are also given and are compared with BF2ion implantation.     

The reverse anneal of junction characteristics in forming shallow p+-n junction by BF2+ implantation intothin Co films on Si substrate

Silicided shallow p⁺-n junctions, formed by BF₂ ⁺ implantation into thin Co films on Si substrates and subsequently annealed, showed a reverse anneal of junction characteristics in the temperature range between 550 and 600°C. The reverse anneal means behavior showing degradation of the considered parameters with increasing annealing temperature. A higher implant dosage caused a more distinct reverse anneal. The reverse anneal of electrical characteristics was associated with the reverse anneal of substitutional boron. A shallow p⁺-n junction with a leakage current density lower than 3 nA/cm₂, a forward ideality factor of better than 1.01, and a junction depth of about 0.1 μm was achieved by just a 550°C anneal     

0.2-μm p+-n junction characteristics dependent onimplantation and annealing processes

Junction depth, sheet resistance, dopant activation, and diode leakage current characteristics were measured to find out the optimal processing conditions for the formation of 0.2-μm p⁺-n junctions. Among the 2×10¹⁵ cm^-2 BF₂ implanted crystalline, As or Ge preamorphized silicon, the crystalline and Ge preamorphized samples exhibit excellent characteristics. The thermal cycle of furnace anneal (FA) followed by rapid thermal anneal (RTA) shows better characteristics than furnace anneal, rapid thermal anneal, or rapid thermal anneal prior to furnace anneal     

6H-SiC p+-n junctions fabricated by berylliumimplantation

The use of beryllium (Be) as an alternate p-type dopant for implanted silicon carbide (SiC) p⁺-n junctions is experimentally demonstrated. The implanted layers have been characterized with photoluminescence (PL) as well as secondary ion mass spectrometry (SIMS) measurements. In comparison with boron implanted p ⁺-n junctions, Be-implanted junctions show improvement in the forward characteristics while exhibiting slightly higher reverse leakages. The activation energies extracted from the forward conduction and reverse leakage characteristics of the Be-diodes are 1.5 eV, and 0.13 eV, respectively. Moreover, activation energy extraction in the forward ohmic region reveals the Be impurity level at 0.38±0.04 eV. The minority carrier lifetime extracted from reverse recovery measurements is as high as 160 ns for the Be-diodes compared to 82 ns obtained for the B-diodes     

p^＋—n^——n结的势垒分布

GaP:N绿色LED发光效率的提高有赖于对其结构参数的优化。根据载流子分布的连续性,由泊松方程自治求解,得出了半导体n^--n结势垒分布的计算方法。在此基础上,计入n^-区内的电位降,计算了商用光二极管p^ -n^--n结构的势垒分布,为整体结构的参数优化准备了必要的条件。     

p+-n junction formed by dual implantation of Zn and As in GaAs junction field-effect transistors

The performance of a p+-n junction formed in GaAs by dual implantation of Zn and As was investigated. The transconductance in linear operation of the junction field-effect transistors (JFET's) in which the p+-gate was formed by the dual implantation was measured and analyzed on a simple one-dimensional model. As the dose of As was increased, the devices showed negatively shifted pinchoff voltage and higher transconductance. It was found that the co-implantation of As significantly decreased the width of the compensated layer in the junction, which improved the JFET's performance.     

Characteristics of polysilicon contacted shallow junction diodeformed with a stacked-amorphous-silicon film

A high-performance shallow junction diode formed with a stacked-amorphous-silicon (SAS) film is presented. Since the boundaries of stacked silicon layers and the poly/mono silicon interface act as a diffusion barrier for implanted dopants, the junction depth of SAS emitter contacted diode is about 500 Å shallower than that of the as-deposited polysilicon emitter contacted diode. The fabricated SAS emitter contacted diodes exhibited a very low reverse leakage current (⩽1 nA/cm² at -5 V) and a forward ideality factor m ≈1.001 over seven decades on a log scale. The reverse I-V characteristics were found to be nearly independent of the reverse voltage from room temperature to 200°C, and it was also found that the leakage current was due almost completely to the diffusion current. The plots of the diode leakage current versus the perimeter to area ratio showed that the periphery-generation current contributed little to the total leakage. The processing temperature for the SAS emitter contacted p⁺-n diode can be as low as 600°C     

Damage removal/dopant diffusion tradeoffs in ultra-shallowimplanted p+-n junctions

The tradeoffs between implant damage annealing and shallow junction formation are investigated. For very-low-energy amorphizing implants the time for damage anneal has a fourth-power dependence on depth below the Si surface. The depth effect depends on the type of amorphizing ion. It is shown that as a result, implanted B in Ge-preamorphized Si diffuses with no detectable self-interstitial supersaturation if the damage is <600 Å deep. Conditions for forming defect-free, shallow p⁺-n junctions are described in design curves and comparisons are made between several junction-formation approaches. Implantation of B at energies below 2 keV offers an attractive way of achieving 500-Å junctions     

Simultaneous formation of silicide ohmic contacts and shallow p+-n junctions by ion-beam mixing and rapid thermal annealing

Low-resistivity, uniform molybdenum silicide layers, and shallow p⁺-n junctions with good electrical characteristics have been formed using ion-beam mixing and rapid thermal annealing (RTA). Detailed reverse leakage current data on RTA annealed diodes, which were formed by implanting BF2⁺into Si substrates through the molybdenum films deposited on Si, are presented. The process has a great potential for CMOS fabrication with self-aligned silicided source, drain, and gate.     

Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

Electrical properties of Ga-implanted Si p+-n shallowjunctions fabricated by low-temperature rapid thermal annealing

p⁺-n shallow-junction diodes were fabricated using on-axis Ga⁶⁹ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1×10¹⁵/cm ², which is in excess of the dosage (2×10¹⁴/cm²) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600°C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm² and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher     

The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

p+-AlInAs/InP junction FETs by selective molecular beamepitaxy

p⁺-AlInAs/InP junction field-effect transistors (FETs) have been fabricated in semi-insulating InP:Fe using ion implantation and a selective molecular-beam epitaxy (MBE) technique. Current-voltage measurements on 4.0-μm gate-length devices show a zero-gate-bias transconductance of 41 mS/mm, and RF measurements indicate a unity-power-gain frequency of 3.2 GHz. These results indicate that the selective growth method is a viable technique for fabricating high-frequency, high-power junction FETs in the InP-based materials system     

A physical model for boron penetration through thin gate oxidesfrom p+ polysilicon gates

Based on numerical device and process simulation, it is shown that enhancement of the boron diffusivity by as much as 300 times in the thin gate oxide results in a very shallow exponential p-type profile in the underlying silicon substrate. The effect of fluorine and phosphorus coimplantation into the p-type polysilicon gate is modeled by changes in the boron diffusivity in the gate oxide and segregation at the polysilicon-oxide interface. An inverse PMOS short-channel behavior in which the threshold voltage becomes more negative with decreasing channel length is modeled by two-dimensional boron segregation effects caused by the poly gate oxidation     

Argon ion-implantation on polysilicon or amorphous-silicon forboron penetration suppression in p+ pMOSFET

In this paper, a technique to use Ar ion-implantation on the p⁺α-Si or poly-Si gate to suppress the boron penetration in p⁺ pMOSFET is proposed and demonstrated. An Ar-implantation of a dose over 5×10¹⁵ cm^-2 is shown to be able to sustain 900°C annealing for 30 min for the gate without having the underlying gate oxide quality degraded. It is believed to be due to gettering of fluorine, then consequently boron, by the bubble-like defects created by the Ar implantation in the p⁺ gate region to reduce the B penetration. Excellent electrical characteristics like dielectric breakdown (E_bd), interface state density (D_it), and charge-to-breakdown (Q_bd) on the gate oxide are obtained. The technique is compatible to the present CMOS process. The submicron pMOSFET fabricated by applying this technique exhibit better subthreshold characteristics and hot carrier immunity